What's New

MathWorks* MATLAB/ Simulink Support

DSP Builder for Intel® FPGAs 18.0 release supports MathWorks* MATLAB/ Simulink 2016b, 2017a, and 2017b.

Intel® Stratix® 10 Device Support

DSP Builder for Intel FPGAs 18.0 release provides major improvements including fMAX gains for Intel Stratix 10 devices. 

RTL Import

RTL import is now supported with the DSP Builder for Intel FPGAs (Advanced Blockset) allowing you to import your existing register transfer level (RTL) into MathWorks MATLAB/ Simulink environment for co-simulation and code generation.

17.1

  • Introduces primary test platform MATLAB R2015b
  • Intel® Stratix® 10 device improvements: reset minimization and pipelining 
  • Minor bug fixes

17.0

  • Intel® Cyclone® 10 device support

Improvements

  • Intel Stratix® 10 device improvements: mapping, fan-out, reset, and CE optimizations for improved fMAX

 

*Comparison based on Stratix V vs. Stratix 10 using Quartus Prime Pro 16.1 Early Beta.  Stratix V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Stratix 10 architecture enhancements of distributed registers in core fabric.  Designs were analyzed using Quartus Prime Pro Fast Forward Compile performance exploration tool.  For more details, refer to HyperFlex FPGA Architecture Overview White Paper: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf.  Actual performance users will achieve varies based on level of design optimization applied.  Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks