Arria® GX FPGAs make designing high-speed serial I/O functionality into your application easy. The design resources listed below provide you with technical information to help you learn about, evaluate, and begin designing with Arria GX FPGAs.
|Device Family Overview||Find the right Arria GX device to meet your design requirements.|
|Arria GX FPGA Applications||Outlines the applications for which Arria GX FPGAs are optimized.|
|High-Speed Serial I/O Solutions Center||Find everything needed for implementing high-speed serial interfaces with Altera® Arria GX FPGAs, including technical documentation, protocols and intellectual property (IP), signal integrity details, and simulation models.|
|Signal Integrity Center||Access Arria GX FPGA signal integrity design resources to help you develop, layout, and verify your high-speed design.|
|Literature Center||Lists all Arria GX FPGA related literature.|
|Quartus® II Software||Learn how Quartus II software supports designing with Arria GX FPGAs.|
|Quartus II Web Edition Software||Download the free Quartus II Web Edition software, which supports all Arria GX devices. No license required.|
|IP MegaStore™||Select off-the-shelf IP core functions from Altera and Altera's partners. IP cores are optimized for Altera devices, reducing design and test time, and can be evaluated in hardware and simulation prior to licensing.|
Quartus® II software delivers the tools and productivity needed for Arria® GX FPGA designs. Quartus II software allows you to exceed your signal integrity targets and complete your design faster for Arria GX FPGAs. Advanced place-and-route technology, physical synthesis, and the Timing Analyzer help you quickly close timing. More details are available in the Quartus II Development Software Handbook.
The Leader in Productivity for Transceiver-Based FPGA Designs
Quartus II software can dramatically improve your productivity compared to traditional high-density FPGA design flows by using the following productivity-enhancing features:
- SOPC Builder is a system-level tool that eliminates mundane and error-prone system integration tasks and allows you to build systems in minutes. Integrate your custom logic and protocol-specific intellectual property (IP) cores without having to manually specify all of the interconnects.
- Timing Analyzer is an ASIC-strength timing analyzer with native support for the industry-standard SDC timing constraints format. The Timing Analyzer offers an easy-to-use GUI, SDC editor, and tool command language (Tcl) console to quickly and easily create timing constraints. In addition, the Timing Analyzer offers fast, interactive timing analysis and reporting to quickly and accurately reach timing closure.
- Push-button physical synthesis technology and the automated Design Space Explorer (DSE) simplify design optimization.
- Extensive cross-probing support between tools helps identify and correct design issues.
- Quartus II software can perform up-front I/O assignment and validation (PDF) so you can begin PCB layout earlier in the design process. You can now change and validate pin assignments at any time without performing a design compilation. The new Quartus II pin planner feature makes it easy to make and manage pin assignments. I/O assignment analysis assists in ensuring optimal signal integrity for your design.
- Complete command-line and Tcl scripting interfaces give you advanced scripting capabilities.
- Industry-leading compile times in Quartus II software are the lowest in the industry.
- Memory requirements in Quartus II software typically are half those required by competing solutions, allowing you to avoid an "out of memory" error during compilation.
- Quartus II software is now built in 32-bit and 64-bit versions for Windows operating systems. Quartus II 64-bit application software allows you to take advantage of computers with more than 4 Gbytes of memory when running Windows XP professional x64.
- Verification solutions include the following features:
- Capability to update memory and constants in-system without reconfiguring the device.
- SignalTap® II embedded logic analyzer and support for integration with external logic analyzers.
- Integration with all leading third-party EDA verification tools and methodologies.
Getting Started With Arria GX FPGAs and Quartus II Software
Arria GX devices are supported in the Quartus II Web Edition software version 7.1 and later. Download the Quartus II Web Edition software and start designing for Arria GX FPGAs today.
- Download Software
- View Webcast
- Get PCIe Core
- Get Reference Design
- Get GbE Core
- Get Device Support
- Get SRIO Core
- Join the Altera Forum
- Get Documentation
- View Knowledge Base
- Use Troubleshooter
- Quartus Prime Software
- Quartus II Development Software Handbook
- Get Handbook (PDF)
- Get Data Sheet (PDF)
- Get Product Catalog (PDF)