Arria® II FPGAs are the lowest power FPGAs with 6.375-Gbps transceivers. Designed for cost-sensitive applications, Arria II FPGAs are based on a 40-nm, full-featured FPGA fabric that includes adaptive logic modules (ALMs), digital signal processing (DSP) blocks, embedded RAM, and a hard PCI Express® IP core. Unlike other 6G transceiver FPGAs, Arria II FPGAs offer improvements in usability that allow you to complete your projects faster.
High-definition (HD) video requirements are driving the demand for greater bandwidth, higher complexity, and triple-rate serial digital interface (SDI). At the same time, the costs associated with broadcast equipment operation and infrastructure are on the rise, driving the demand for lower power and smaller-footprint products.
Traditional component solutions such as ASSPs provide no opportunity for greater integration or product differentiation, and full custom ASICs can be too risky, requiring large capital investment and lengthy development times that can make your product late to market.
Arria® II FPGAs with transceivers enable you to meet the demand for increasingly complex, highly integrated products that deliver 3G-SDI and other high-speed serial protocols, combined with high-performance custom video processing, lower power, and smaller physical footprints (see Figure 1 for a typical Arria II broadcast application). Only Arria II FPGAs provide the right combination of flexibility, ease of development, rapid time to market, and industry-leading transceiver technology to make your product development as smooth and as fast as possible.
Investigate our Arria II FPGA-based broadcast solutions for yourself, including the SDI MegaCore® function and Arria II GX development kits (3G and 6G editions), and find out why broadcast industry leaders rely on Altera for their programmable logic needs. For the latest details on the Arria II GX development kits, contact your local Altera Sales Representative.
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Military application functions that were once restricted to ASIC designs or microprocessor systems now benefit from the shorter design cycle times and simpler hardware verification processes of an FPGA. Our 40-nm Arria® II FPGAs, in particular, are ideal for military applications. Arria II FPGAs feature integrated transceivers at speeds up to 6.375 Gbps, rich memory and logic resources, and digital signal processing (DSP) capabilities.
The following figure conveys the growing list of military electronics design domains that can be addressed with programmable logic devices.
The effect is a greater potential for system-on-chip (SoC) integration with an emphasis on tool flow and intellectual property (IP) reuses. This is especially true given the more difficult verification and rigorous test requirements of military electronics systems.
While the number of technical requirements that must be considered by systems engineers cannot be easily summarized, there are three large initiatives in military electronics technology that are addressed by Arria II FPGAs: reductions in size, weight, and power (SWaP).
The simplest approach to reducing SWaP is integrating many subsystems into a single chip. While this can be enabled through robust systems engineering processes and workflow controls, it increases the importance of open systems designs and anti-tamper technologies for FPGAs. To see effiiciency improvements in new SoC designs, design re-uses must be a fundamental part of systems design flow.
The Altera® design flow makes standard interface IP available throughout the design entry process. This includes the high-speed Serial Rapid IO® standard, both soft and hard PCI Express cores, Gigabit Ethernet, and 10 Gigabit Ethernet cores optimized for Altera’s transceiver technology. For your own internally developed IP cores, encapsulation of these cores in Altera’s Qsys system integration tool is a simple process that allows for easy archival and retrieval of important re-usable logic blocks.
While there are plenty of reasons to focus on the features and capabilities of Arria II FPGAs, cost conscious military systems designers must also evaluate design flow. Design time productivity for programmable devices includes verification, debug, and compile times, which can all present significant schedule risks in defense programs. As a result, Altera has invested significantly in compile-time improvements, multiprocessor synthesis support, and incremental compile technology to include team-based “bottoms up" design, and the Qsys tool for fast system bus generation.
New wireless standards such as 3G and Long Term Evolution (LTE) are increasing digital signal processing (DSP) needs while adding pressure to reduce overall system costs. Operating and maintenance costs of equipment often placed in remote locations drive stringent energy consumption requirements. Although equipment is often placed in thermally challenging environments, active cooling solutions such as fans are not allowed because of reliability concerns.