The design resources listed below provide you with technical information to help you successfully design with Arria® II FPGAs. For full details on devices in the Arria II FPGA family, see the Arria II FPGA Overview page.
|Software Tools and Development Kits||Intellectual Property and Design Examples|
|End-Market Applications||Online Training and Webcasts|
Take advantage of the many resources available, including example designs, documentation, and software, to help you quickly implement designs using Arria® II FPGAs.
Table 1. Using Arria II FPGAs
|Quartus® II Subscription Edition Software||Complete suite of design software to enable your Arria II FPGA design.|
|User Guides and Tutorials|
|Arria II Handbook||Download this comprehensive technical information guide to the Arria II FPGA family.|
|PCI Express Hard IP Quick Start Guide with SOPC Builder||A video tutorial that shows you how to use the tools to quickly get a PCIe design up and running.|
|PCI Express||Provides details on solutions for PCIe targeting Arria II FPGAs.|
|Serial RapidIO®||Provides details on solutions for Serial RapidIO targeting Arria II FPGAs.|
|Gigabit Ethernet||Provides details on solutions for Gigabit Ethernet targeting Arria II FPGAs.|
|10-Gigabit Ethernet||Provides details on solutions for 10-Gigabit Ethernet targeting Arria II FPGAs.|
|SDI||Provides details on solutions for SDI targeting Arria II FPGAs.|
|HiGig||Provides details on solutions for HiGig targeting Arria II FPGAs.|
|CPRI||Provides details on solutions for CPRI targeting Arria II FPGAs.|
|OBSAI||Provides details on solutions for OBSAI targeting Arria II FPGAs.|
|GPON||Provides details on solutions for GPON targeting Arria II FPGAs.|
|SONET||Provides details on solutions for SONET targeting Arria II FPGAs.|
|Reference Designs, Application Notes, and White Papers for Arria II GX FPGAs|
PCI Express High Performance Reference Design
|The PCI Express high-performance reference design uses the Arria II PCIe hard IP block and includes a high-performance chaining direct memory access (DMA) that transfers data between the FPGA's internal memory and the system memory. The design includes a Windows XP-based software application that sets up the DMA transfers. The software application also measures and displays the performance achieved for the transfers.|
|10-Gigabit Ethernet Reference Design
- Application Note
|The Altera 10-GbE reference design consists of a 10-GbE MAC IP. This design provides a XAUI external interface to easily connect the system logic to a variety of standard 10-GbE PHY devices and optical transceiver modules.|
|Presents the challenges of Triple-Rate SDI and illustrates a sample loopback design for Arria II GX FPGAs. The reference design is delivered through the MegaWizard Plug-In Manager in Quartus II software.|
|DUC and DDC Digital IF Modem Reference Design for WiMAX
- Application Note
Presents the tool flow for implementing a Digital IF Modem design for WiMAX. The application note has details on how to load the design from Quartus II software tools. In addition to Quartus II software version 9.0 or later, you'll need the following programs:
|Arria II Development Kits||
Altera and partners provide a range of development kits supporting multiple protocols and peripherals to get you up and running quickly.
Resources for developing and prototyping transceiver-based applications up to 6.375 Gbps.