The 40-nm Arria® II FPGA family delivers the lowest power FPGA with 6.375-Gbps transceivers for cost-sensitive applications.

Arria II Device Family Variations

Variant Description
Arria II GX Arria II GX FPGAs have up to 16 6.375-Gbps transceivers, LVDS at 1.25 Gbps, and support for 400 MHz DD3.  
Arria II GZ Arria II GZ FPGAs offer up to 24 6.375-Gbps transceivers, more density and memory, and higher digital signal processing (DSP) capabilities than Arria II GX FPGAs.
classtest

Lowest Power FPGAs with Up to 6.375-Gbps Transceivers

Altera's cost-optimized Arria® II FPGAs deliver the lowest power of any FPGA with up to 6.375-Gbps transceivers. Built on the 40-nm process node, Arria II FPGAs offer higher usability and efficiency for designs in the mid-range category.

Arria II Architecture

Arria® II FPGAs, Altera’s cost-optimized, low-power 40-nm FPGAs with transceivers, leverage many of the same architectural benefits as Altera’s latest high-end Stratix® families. This allows you to achieve excellent logic utilization, easily meet timing, and reduce power requirements for your system.

The tables below provide an overview of the Arria II FPGA family and package choices, respectively. Table 5 provides information on the industrial temperature support.

Table 1. Arria II GZ FPGA Family Overview (1)

Features EP2AGZ225 EP2AGZ300 EP2AGZ350
Adaptive Logic Modules (ALMs)89,600119,200139,400
Equivalent LEs224,000298,000348,500
M9K Memory Blocks/Mb1,235/11.11,248/11.21,248/11.2
M144K Memory Blocks / Mb-24 / 3.436 / 5.2
Total Memory (M9K+M144K in Mb)11.114.616.4
18-Bit x 18-Bit Embedded Multipliers8009201,040
Maximum Transceivers242424
PCI Express Hard IP Blocks111
Maximum User I/O Pins726726726
AvailabilityContact AlteraContact AlteraContact Altera
classtest

Table 2. Arria II GX FPGA Family Overview (2)

Features EP2AGX45 EP2AGX65 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260
Adaptive Logic Modules (ALMs)18,05025,30037,47049,64076,120102,600
Equivalent LEs45,12563,25093,674124,100190,300256,500
M9K Memory Blocks/Mb319/2.9495/4.5612/5.5730/6.6840/7.6950/8.5
Total Memory (M9K + MLAB in Mb)3.45.36.78.19.911.8
18-Bit x 18-Bit Embedded Multipliers232312448576656736
PLLs446666
Maximum Transceivers8812121616
PCI Express Hard IP Blocks111111
Maximum User I/O Pins364364452452612612
AvailabilityBuy NowBuy NowBuy NowBuy NowBuy NowBuy Now
classtest

Table 3. Arria II GZ FPGA Package Overview and User I/Os (LVDS, Transceivers) (3)

Device H780
1.0 mm
(33 x 33)
F1152
1.0 mm
(35 x 35)
F1517
1.0 mm
(40 x 40)
EP2AGZ225-550 (42, 16)726 (86, 24)
EP2AGZ300268 (0, 16)550 (42, 16)726 (86, 24)
EP2AGZ350268 (0, 16)550 (42, 16)726 (86, 24)
classtest

Table 4. Arria II GX FPGA Package Overview and User I/Os (LVDS, Transceivers) (3)

Device U358
0.8 mm
(17 x 17)
F572
1.0 mm
(25 x 25)
F780
1.0 mm
(29 x 29)
F1152
1.0 mm
(35 x 35)
EP2AGX45156 (33, 4)252 (57, 8)364 (85, 8)-
EP2AGX65156 (33, 4)252 (57, 8)364 (85, 8)-
EP2AGX95-260 (57, 8)372 (85, 12)452 (105, 12)
EP2AGX125-260 (57/56, 8)372 (85, 12)452 (105, 12)
EP2AGX190--372 (85, 12)612 (145, 16)
EP2AGX260--372 (85, 12)612 (145, 16)
classtest

Notes:

  1. Arria II GZ devices are offered in -3 and -4 speed grades.
  2. Arria II GX devices are offered in -3, -4, -5, and -6 speed grades. -3 only available in industrial grade. Please refer to the Arria II Device Handbook for details.
  3. Pin migration within each package.

Table 5. Industrial Temperature Support

Device Package Speed Grade
Arria II GZH780, F1152, F1517I3, I4
Arria II GXU358 (1), F572, F780, F1152I3, I5
classtest