Arria® V Device Family Variations

Feature Arria V GZ FPGA Arria V GT FPGA Arria V GX FPGA Arria V ST SoC Arria V SX SoC
ALMs (K) 170 190 190 174 174
Variable-Precision DSP 1,139 1,156 1,156 1,068 1,068
M20K Blocks 1,700 - - - -
M10K Blocks - 2,414 2,414 2,282 2,282
DDR3 Memory Interface Speed 800 MHz 667 MHz 667 MHz 667 MHz 667 MHz
Hard Memory Controllers - 4 4 4 4
Transceivers (Gbps) 12.5 Gbps 10.3125 6.5536 10.3125 6.5536
PCI Express® (PCIe) Gen3/2/1 hardened IP block 1 - - - -
PCIe Gen2/1 hardened IP blocks(s) - 2 2 2 2
Design Security          
Single Event Upset (SEU) Mitigation          

Flexible Transceivers

Whether you need a few channels of transceivers, or up to 36, Arria® V FPGAs provides transceiver solutions to meet your performance and power requirements to deliver exactly what you need to succeed.

Variable-Precision DSP Block

Arria V FPGAs and SoCs feature the industry's first variable-precision digital signal processing (DSP) block. This integrated block, part of Altera's 28 nm FPGA DSP portfolio, allows you to configure each block into an 18-bit mode or in a high-precision mode at compile time.

SoC FPGA Hard Processor System

Altera SoCs integrate an ARM®-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. The Arria® V SoCs reduce system power, system cost, and board size while increasing system performance by integrating discrete processor, FPGA, and digital signal processing (DSP) functions into a single, user customizable ARM-based system on a chip (SoC). SoCs provide the ultimate combination of hardened intellectual property (IP) for performance and power savings, with the flexibility of programmable logic.

Arria V SoC Block Diagram

HPS Features

  • Each processor core includes:
    • 32 KB of L1 instruction cache, 32 KB of L1 data cache
    • Single- and double-precision floating-point unit and NEONTM media engine
    • CoreSightTM debug and trace technology
  • 512 KB of shared L2 cache with error correction code (ECC) support
  • 64 KB of scratch RAM with ECC support
  • Multiport SDRAM controller with support for DDR2, DDR3, and LPDDR2 as well as optional ECC support
  • 8-channel direct memory access (DMA) controller
  • QSPI flash controller
  • NAND flash controller with DMA
  • SD/SDIO/MMC controller with DMA
  • 2x 10/100/1000 Ethernet media access control (MAC) with DMA
  • 2x USB On-The-Go (OTG) controller with DMA
  • 4x I2C controller
  • 2x UART
  • 2x serial peripheral interface (SPI) master peripherals, 2x SPI slave peripherals
  • Up to 134 general-purpose I/O (GPIO)
  • 7x general-purpose timers
  • 4x watchdog timers

High-Bandwidth HPS-to-FPGA Interconnect Backbone

Although the HPS and the FPGA can operate independently, they are tightly coupled via a high-bandwidth system interconnect built from high-performance ARM AMBA® AXITM bus bridges. IP bus masters in the FPGA fabric have access to HPS bus slaves via the FPGA-to-HPS interconnect. Similarly, HPS bus masters have access to bus slaves in the FPGA fabric via the HPS-to-FPGA bridge. Both bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. An additional 32-bit light-weight HPS-to-FPGA bridge provides low latency interface between the HPS and peripherals in the FPGA fabric. Up to six FPGA masters can share the HPS SDRAM controller with the processor. Additionally, the processor can be used to configure the FPGA fabric under program control via a dedicated 32-bit configuration port.

  • HPS-to-FPGA: configurable 32-, 64-, or 128-bit AMBA AXI interface optimized for high bandwidth
  • FPGA-to-HPS: configurable 32-, 64-, or 128-bit AMBA AXI interface optimized for high bandwidth
  • Lightweight HPS-to-FPGA: 32-bit AMBA AXI interface optimized for low latency
  • FPGA-to-HPS SDRAM controller: configurable multi-port interfaces with 6 command ports, 4x 64-bit read data ports and 4x 64-bit write data ports
  • ~32-bit FPGA configuration manager

The 28 nm Arria® V FPGA family offers the lowest power, highest bandwidth FPGAs for mid-range applications, such as remote radio units, 10G/40G line cards, and in-studio mixers. A comprehensive offering of five device variants allows designers to optimally choose a solution that meets their price, performance, and power requirements. See the tables below for an overview of the Arria V FPGA and SoC family and package choices.  

Arria V GX FPGA Family Overview

Features 5AGXA1 5AGXA3 5AGXA5 5AGXA7 5AGXB1 5AGXB3 5AGXB5 5AGXB7
Equivalent logic elements (LEs) (K) 75 156 190 242 300 362 420 504
Adaptive logic modules (ALMs) 28,302 58,900 71,698 91,680 113,208 136,880 158,491 190,240
M10K memory blocks 800 1,051 1,180 1,366 1,510 1,726 2,054 2,414
M10K memory (Kb) 8,000 10,510 11,800 13,660 15,100 17,260 20,540 24,140
Memory logic array blocks
(MLABs) (Kb)
463 961 1,173 1,448 1,852 2,098 2,532 2,906
18x18 multipliers 480 792 1,200 1,600 1,840 2,090 2,184 2,312
Variable-precision
digital signal processing (DSP) blocks
240 396 600 800 920 1,045 1,092 1,156
Maximum transceivers
6.5536 Gbps
9 9 24 24 24 24 36 36
PCI Express® (PCIe®)
hardened intellectual property (IP) block(s)
1 1 2 2 2 2 2 2
Maximum user I/O pins 416 416 544 544 704 704 704 704
Notes:

Arria V GX devices are offered in -3, -4, -5, and -6 speed grades.  

Arria V GX FPGA Package Overview and User I/O Pins (I/O Pins, Transceivers)

Device 5AGXA1 5AGXA3 5AGXA5 5AGXA7 5AGXB1 5AGXB3 5AGXB5 5AGXB7
F672
(27 mm)
336, 9 336, 9 336, 9 336, 9 - - - -
F896
(31 mm)
416, 9 416, 9 384, 18 384, 18 384, 18 384, 18 - -
F1152
(35 mm)
- - 544, 24 544, 24 544, 24 544, 24 544, 24 544, 24
F1517
(40 mm)
- - -   704, 24 704, 24 704, 36 704, 36

Arria V GT FPGA Family Overview (1)

Features 5AGTC3 5AGTC7 5AGTD3 5AGTD7
Equivalent LEs (K) 156 242 362 504
ALMs 58,900 91,680 136,880 190,240
M10K memory blocks 1,051 1,366 1,726 2,414
M10K memory (Kb) 10,510 13,660 17,260 24,140
MLABs (Kb) 961 1,448 2,098 2,906
18x18 multipliers 792 1,600 2,090 2,312
Variable-precision
DSP blocks
396 800 1,045 1,156
Maximum transceivers
(6.5536 Gbps / 10.3125 Gbps)(2)(3)
9 / 4 24 / 12 24 / 12 36 / 20
PCIe hardened IP block(s) 1 2 2 2
Maximum user I/O pins 416 544 704 704
Notes:
  1. Arria V GT devices are offered in the -5 and -3 speed grades.
  2. 10 Gbps transceivers are for chip-to-chip connections only.
  3. Each set of three 6.5536 Gbps transceivers can be configured as two 10.3125 Gbps transceivers with the exception of one set in the F672 package and two sets in all other packages which have a maximum rate of 6.5536 Gbps.

Arria V GT FPGA Package Overview and User I/O Pins (I/O Pins, Maximum 6 Gbps Transceivers, Maximum 10 Gbps Transceivers) (1) (2)

Device 5AGTC3 5AGTC7 5AGTD3 5AGTD7
F672
(27 mm)
336, 9, 4   - -
F896
(31 mm)
416, 9, 4 384, 18, 8 384, 18, 8 -
F1152
(35 mm)
- 544, 24, 12 544, 24, 12 544, 24, 12
F1517
(40 mm)
-   704, 24, 12 704, 36, 20
Notes:
  1. Pin migration within each package.
  2. Each set of three 6.5536 Gbps transceivers can be configured as two 10.3125 Gbps transceivers with the exception of one set in the F672 package and two sets in all other packages which have a maximum rate of 6.5536 Gbps.

Arria V GZ FPGA Family Overview

Features 5AGZE1 5AGZE3 5AGZE5 5AGZE7
Equivalent LEs (K) 220 360 400 450
ALMs 83,020 135,840 150,960 169,800
M20K memory blocks 585 957 1,440 1,700
M20K memory (Kb) 11,700 19,140 28,800 34,000
MLABs (Kb) 2,954 4,245 4,718 5,306
18x18 multipliers 1,600 2,088 2,184 2,278
Variable-precision DSP blocks 800 1,044 1,092 1,139
Maximum transceivers up to 12.5 Gbps 24 24 36 36
PCIe hardened IP block(s) 1 1 1 1
Maximum user I/O pins 414 414 674 674

Arria V GZ FPGA Package Overview, Transceivers and User I/O Pins

Device 5AGZE1 5AGZE3 5AGZE5 5AGZE7
F780
(29 mm)
342, 12 342, 12 - -
F1152
(35 mm)
414, 24 414, 24 534, 24 534, 24
F1517
(40 mm)
-   674, 36 674, 36

Arria V SX SoC Family Overview

Features 5ASXB3 5ASXB5
Equivalent LEs 350,000 462,000
ALMs 132,075 174,340
M10K memory blocks 1,729 2,282
M10K memory (Kb) 17,288 22,820
MLABs (Kb) 2,014 2,658
18x19 multipliers 1,618 2,180
Variable-precision DSP blocks 809 1,090
Maximum transceivers 6.5536 Gbps 30 30
PCIe hardened IP block(s) 2 2
Maximum FPGA user I/Os 540 540
Maximum HPS I/Os 208 208
FPGA hardened memory controllers 3 3
HPS hardened memory controllers 1 1
Processor cores (ARM® Cortex®-A9) Dual Dual

Arria V SX SoC Package Overview and User I/O Pins (FPGA IO, HPS I/O Pins Transceivers)

Device/Package
(mm x mm)
F896 F1152 F1517
1.0 mm
31 x 31
1.0 mm
35 x 35
1.0 mm
40 x 40
FPGA I/Os HPS I/Os Maximum Transceivers
(6.5536 Gbps)
FPGA I/Os HPS I/Os Maximum Tranceivers
(6.5536 Gbps)
FPGA I/Os HPS I/Os Maximum Transceivers
(6.5536 Gbps)
5ASXB3 250 208 12 385 208 18 540 208 30
5ASXB5 250 208 12 385 208 18 540 208 30

Arria V ST SoC Family Overview

Features 5ASTD3 5ASTD5
Equivalent LEs 350,000 462,000
ALMs 132,075 174,340
M10K memory blocks 1,729 2,282
M10K memory (Kb) 17,288 22,820
MLABs (Kb) 2,014 2,658
18x19 multipliers 1,618 2,180
Variable-precision DSP blocks 809 1,090
Maximum transceivers (6.5536 Gbps / 10.3125 Gbps)(1) (2) 30 / 16 30 / 16
PCIe hardened IP block(s) 2 2
Maximum FPGA user I/Os 540 540
Maximum HPS I/Os 208 208
FPGA hardened memory controllers 1 1
HPS hardened memory controllers 3 3
Processor cores (ARM Cortex-A9) Dual Dual
Notes:
  1. 10 Gbps transceivers are for chip-to-chip connections only.
  2. Each set of three 6.5536 Gbps transceivers can be configured as two 10 Gbps transceivers with the exception of the two sets nearest the PCIe hard IP which have a maximum rate of 6.5536 Gbps.

Arria V ST SoC Package Overview and User I/O Pins (I/Os Pins, Transceivers)

Device/Package
(mm x mm)
F896 F1152 F1517
1.0 mm
31 x 31
1.0 mm
35 x 35
1.0 mm
40 x 40
FPGA I/Os HPS I/Os Maximum Transceivers
(6.5536 Gbps / 10.3125 Gbps)
FPGA I/Os HPS I/Os Maximum Transceivers
(6.5536 Gbps / 10.3125 Gbps)
FPGA I/Os HPS I/Os Maximum Transceivers
(6.5536 Gbps / 10.3125 Gbps)(1)
5ASTD3 250 208 12 / 6 385 208 18 / 8 540 208 30 / 16
5ASTD5 250 208 12 / 6 385 208 18 / 8 540 208 30 / 16
Notes:
  1. Each set of three 6.5536 Gbps transceivers can be configured as two 10 Gbps transceivers with the exception of the two sets nearest the PCIe hard IP which have a maximum rate of 6.5536 Gbps.

Temperature Support

Device Package Speed Grade
Arria V GZ F780, F1152, F1517 C3, C4, I3L, I4
Arria V SX/GX/ST/GT F672, F896, F1152, F1517 C4, C5, C6, I3, I5