Intel® Cyclone® 10 GX FPGAs deliver high perfomance in a low-cost FPGA. Learn more about the capabilities and advantages that are offered by the Intel Cyclone 10 GX device family.
Intel Cyclone 10 GX FPGA has adopted a column I/O structure with the 12.5 Gbps transceivers on the left-hand side of the die, and the GPIO in vertical columns in banks of 48 I/Os, each with a high-efficiency memory controller and I/O phase-locked loop (PLL). Each GPIO bank also supports LVDS pairs, with each pair having differential input and output buffers allowing users to configure the LVDS direction for each pair at 1.4 Gbps.
In Intel® Cyclone® 10 GX devices, Intel has enhanced the variable-precision digital signal processing (DSP) block used in Cyclone V FPGAs by including hardened floating-point operators in the Intel Cyclone 10 GX device DSP block. The Intel Cyclone 10 GX FPGA variable-precision DSP block introduces a new floating-point mode that delivers breakthrough floating-point performance .
With the three modes available for Intel Cyclone 10 GX device DSP blocks: standard-precision fixed-point (18 bit fixed-point mulitpliers), high-precision fixed-point (27 bit fixed-point mulitpliers), and single-precision floating-point, designers can implement a variety of algorithms that require fixed point all the way to double-precision IEEE 754 compliant floating-point operations. Hardened floating-point processing offers designers the ability to implement algorithms in floating point with the similar performance and power efficiency as fixed point. This can be achieved without any power, area, or density compromises and with no loss of fixed-point features or functionality.
Intel® Cyclone® 10 GX devices provide an efficient architecture that allows up to 72 bit wide of DDR3 memory interfaces at up to 1,866 Mbps to support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are designed to provide high-performance support for existing and emerging external memory standards.
Compared to previous generation of Cyclone FPGAs, the new architecture and solution provide the following advantages:
- Pre-closed timing in the controller and from the controller to the PHY
- Easier pin placement
For maximum performance and flexibility, the architecture offers hard memory controller and hard PHY for key interfaces.
- The solution offers completely hardened external memory interfaces for several protocols
- The devices feature columns of I/Os that are mixed within the core logic fabric instead of I/O banks on the device periphery
- A single hard Nios® II processor block calibrates all the memory interfaces in an I/O column
- The I/O columns are composed of groups of I/O modules called I/O banks
- Each I/O bank contains a dedicated integer PLL (IO_PLL), hard memory controller, and delay-locked loop
- The PHY clock tree is shorter compared to previous generation Cyclone devices and only spans one I/O bank
Single-event upsets (SEUs) are rare, unintended changes in the state of internal memory elements caused by cosmic radiation effects. The change in state results in a soft error and there is no permanent damage to the device.
Intel® Cyclone® 10 GX FPGAs ensure high reliability and with specific SEU mitigation capabilities.
- Advanced SEU detection (ASD) and correction
- Error detection CRC scrubbing with automatic correction
- Sensitivity processing
- Hierarchy tagging
- Error detection CRC scrubbing with automatic correction
- Fault injection
- Use to characterize, test, and improve your designs
Intel® Cyclone® 10 GX devices offer up to 12 low-latency transceiver channels with integrated advanced high-speed analog signal conditioning and clock data recovery techniques for chip-to-chip applications.
Offering a maximum frequency of 12.5 Gbps per transceiver I/O for chip-to-chip communications, the Intel Cyclone 10 GX device enables higher rate protocols, such as GigE Vision, USB3.1, CoaXPress, Camera Link, DisplayPort 1.3, and HDMI in a low-cost solution. Intel Cyclone 10 GX devices also supports backplane driving at data rates up to 6.6 Gbps.
A column array of transceiver I/O banks on the left-side periphery of the device, each bank contains six transceiver channels. Intel Cyclone 10 GX devices also include a PCI Express* Gen2 Hard IP block for applications, such as connecting to an external Intel processor.
Nios® II processor, the world's most versatile, royalty-free processor according to Gartner Research is the most widely used soft processor in the FPGA industry. The Nios II processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), and ASIC-optimized applications processing needs.
The Nios II processor family consists of two configurable 32 bit Harvard architecture cores:
- Fast (/f core): Six-stage pipeline optimized for highest performance, optional memory management unit (MMU), or memory protection unit (MPU)
- Economy (/e core): Optimized for smallest size, and available at no cost (no license required)
Need to boost performance? No problem. Hardware acceleration is as easy as using an FPGA's programmable logic to offload and accelerate tasks that are typically implemented in an application software. Find out more on the Nios II Processor web page.
For more information on free software development tools, visit the Nios II Processor Design Tools web page.
For more information on Nios II processor architecture, visit the Nios II Processor Overview web page.
For Nios II processor training, visit the Intel® FPGA Technical Training web page.
Table 1. Processor Performance
|Variant||Performance (DMIPS at fMAX)1†|
|Nios II / e Economy||52.5 at 350 MHz1†|
|Nios II / f Fast||305 at 270 MHz1†|
1 Dhrystonmes 2.1 benchmark (Intel Estimate)
Table 2. Processor Applications
|Application||Nios II Processor Core||Vendor||Description|
|Power and cost sensitive||Nios II economy core||Intel||With as low as 600 logic elements, the Nios II economy processor core is ideal for microcontroller applications. The Nios II economy processor core, software tools, and device drivers are offered free of charge.|
|Real Time||Nios II fast Core||Intel||
Absolutely deterministic, jitter-free real-time performance with the following unique hardware real-time feature options:
|Applications processing||Nios II fast core||Intel||With a simple configuration option, the Nios II fast processor core can use a memory management unit (MMU) to run embedded Linux. Both open source and commercially supported versions of Linux for Nios II processors are available.|
|Safety Critical||Nios II SC core||HCELL||Certify your design for DO-254 compliance by using the Nios II Safety Critical processor core along with the DO-254 compliance design services offered by HCELL.|
|Lockstep Dual Core||fRSmartComp IP||Yogitech||The lockstep solution provides high diagnostic coverage, self-checking, and advanced diagnostic features in full compliance with functional safety standards IEC 61508 and ISO 26262 while reducing the need for difficult-to-develop and performance-sapping diagnostic software test libraries.|
Take full advantage of Intel® Cyclone® 10 GX FPGAs performance without sacrificing efficiency with Intel Enpirion® power solutions.
Intel® Enpirion® power solutions are highly efficient power management products featuring small size, leading-edge silicon and magnetics design, advanced packaging, and fully validated designs.
The ultra-compact and efficient PowerSoCs from the Intel Enpirion power solution series are ideal for meeting Intel Cyclone 10 GX FPGAs power requirements. Intel Enpirion PowerSoCs integrate nearly all the components needed for Intel Cyclone 10 GX FPGAs power rails, providing a family of fully validated, easy-to-use solutions with up to 96% efficiency†. This will free up designers time so that they can focus on their unique intellectual property (IP) and FPGA designs, and spend less time on power supply design.
To find our more, visit the Powering FPGAs web page.
Intel® Cyclone® 10 GX FPGAs are offered in extended commercial and industrial device grades. In addition, they will be supported in a future release of the functional safety pack, TUV Certified to IEC 61508 reducing development time and time to market.
1 Compared to previous generation Cyclone FPGAs, cost comparisons are based on list price.
† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.