I/O Expansion

The increasing performance requirements of today's embedded systems is driving microprocessor selection. Processor performance, coupled with their fixed interfaces often influences selection of larger processor than required in order to support the I/O feature set that the system requires. An alternative option is to use an optimal processor with a companion FPGA for I/O expansion to enable more functions.

Intel® Cyclone® 10 LP FPGAs are ideally suited to this kind of application, with a range of IP blocks, such as I2C, serial peripheral interface (SPI), UART and parallel I/O blocks all available, along with packages supporting over 500 I/O. Enabling the designer to scale his design to fit the applications needs, rather than limiting either his design to a fixed processor peripheral set or increasing system cost with a larger processor.

Chip to Chip Interfacing

Intel® Cyclone® 10 LP FPGAs are an ideal solution for interfacing between ASSPs. Examples such as between an image sensor and host processors or between the processor and and display. In both of these scenarios using an FPGA such as Intel Cyclone 10 LP enable designers to combine the interfacing with image pipeline processing for real-time applications which need high frame rates, low latency, and high processing throughput.

One example application is where a CMOS image sensor capture raw images and output the data via several different type of interfaces: DVP, MIPI CSI, or HiSPi to the FPGA. The FPGA is used to process the image before passing data onto a host processor. A second example of chip to chip interfacing is where the FPGA is used to interface between a video source and LCD. Where video processing of the input image data may be required for various reasons and may be implmented usng the Video IP suite from Intel for functions such as:

  • Demosaic & bayer filtering
  • Converting from one data format to another, example: YUV à RGB
  • Scaling from one size to another: example: 1280x720 à 1920x1080
  • Encoding/decoding, filtering, blending, de/interlacing, cropping, etc.

 

 

Motor Control

Intel® Cyclone® 10 LP  FPGAs provides the flexibility for general-purpose interfacing (with a maximum I/O count up to 525 user I/Os) and the ability not to only support our customers' diverse drive needs, but also to differentiate their high-volume applications.

In addition to facilitating the implementation and support for a wide variety of industrial Ethernet protocols. The Intel Cyclone 10 LP FPGA fabric is also leveraged to implement PWM and encoder interfaces, which when repeated parallelly multiple times, allows for multi-axis control.

Intel's Field Oriented Control (FOC) algorithm along with the Vibration Suppression IP Core implemented on the Intel Cyclone 10 LP FPGA fabric enables performance acceleration, latency reduction and the option to off-load and free up the Nios II processor for other tasks

Additional End Markets

For more information on how to use Intel Cylone 10 LP FPGAs in other applications, refer to the following pages :