Cyclone II Cost-Optimized Architecture

Building on the success of Cyclone® devices, Altera introduces Cyclone II, the lowest-cost 90-nm FPGAs ever. Cyclone II devices enable the development of new, programmable solutions in cost-sensitive applications where FPGAs were once considered too expensive.

If you need even lower costs, larger density, and greater functionality for high-volume applications, you can take advantage of 65-nm Cyclone III FPGAs.

Challenges of Cost Optimization

When designing low-cost FPGAs, you need to address the tradeoff between performance, features, and overall device cost. You need to ensure sufficient logic and memory density for a complete solution while providing adequate performance at reasonable prices (Figure 1).

Altera helps you meet these needs by creating an architecture that provides optimal performance for its target applications. By designing Cyclone II FPGAs to match the performance of the original Cyclone family, Cyclone II devices provide the benefits of 90-nm technology (small die size, high density, and low cost) with the fastest performance in low-cost FPGAs. All Cyclone II devices are manufactured on 300-mm wafers using TSMC's 90-nm low-k dielectric process technology.

Figure 1. Balancing Power, Performance, and Cost

Getting Much More for Much Less

To develop FPGAs that successfully reach its low-cost goals for high-volume applications, Altera adopted a new design methodology. The traditional "optimization-by-elimination" approach involves reducing the cost of an existing high-density product by eliminating features in software. Although this method is marginally effective in reducing FPGA cost, it does not attain the lowest possible price points for a given die size and package.

In contrast, the design methodology Altera used to build Cyclone and Cyclone II devices did not rely on the re-purposing of existing products. Similar to the process used for the first-generation Cyclone architecture, the Cyclone II architecture definition focused on building for low cost from the start.

Cyclone II devices are pad limited. A pad-limited die means that the I/O structure is as small as possible, and therefore the die cost is at its lowest. In some devices, Cyclone II devices offer staggered I/O pads, meaning that two rows of I/O pads are interleaved, increasing the number of available I/O pads.

Cyclone II devices were built starting with the careful selection of small form-factor packages that offer sufficient user I/O pins and the lowest-cost structure. From the physical dimensions of the package, the maximum size of a pad-limited die can be determined. The logic is then populated with as many logic elements (LEs), memory blocks, embedded multiplier blocks, and other customer-requested features as possible, guaranteeing the most functionality in the available area.

The routing structures in Cyclone II FPGAs have been enhanced to increase their efficiency. The logic array block (LAB) contains 16 LEs, instead of 10 LEs for the original Cyclone family. At 90 nm, routing contributes more to the on-chip delays than the LE. By having a 16 LE LAB, the amount of routing is reduced, and performance can be improved.

Cyclone II Architecture

The Cyclone II architecture consists of more than 68K vertically arranged LEs, embedded memory blocks, embedded multipliers, and phase-locked loops (PLLs) that are surrounded by I/O elements (IOEs) (Figure 2). A highly efficient interconnect and low-skew clock network provides connectivity between each of these structures for clock and data signals.

Figure 2. Cyclone II Floorplan

Area-efficient IOEs are grouped into I/O banks around the device, offering significant capabilities while consuming minimal die area. Cyclone II devices support a wide range of single-ended and differential I/O standards, such as the LVDS I/O standard at up to 805 Mbps (receive) and 622 Mbps (transmit). Each IOE contains three registers for implementing DDR applications and associated circuitry for other I/O features such as programmable drive strength, bus hold, and programmable slew rate.

Several I/O banks are equipped with dedicated external memory interface circuitry. This circuitry simplifies data transfer with external memory devices, including DDR2 and QDRII SDRAM devices. Maximum data transfer rates reach speeds of up to 333 Mbps (167-MHz clock).

Cyclone II devices implement the same embedded memory blocks available in the original Cyclone family. The Cyclone II family includes up to 250 embedded memory blocks, which are ideal for use as program storage memory for embedded processors or header or cell storage.

Cyclone II devices are PCI revision 2.1 and PCI-X revision 1.0b (Rev 2.0 mode 1) compliant. Each IOE provides multiple paths from the pin to the core, allowing the device to meet associated set-up and hold times.

Cyclone II devices range in density from 4,608 LEs and 119,808 bits of RAM to 68,416 LEs and 1,152,000 bits of RAM. From 13 to 150 18 x 18 embedded multipliers are available within Cyclone II devices. More information is available on the Cyclone II overview page.

Clock Distribution

Each Cyclone II device is served by a global clock network composed of up to sixteen distinct clock lines. These clock lines are accessible from anywhere in the device and can be fed either by input pins, PLL outputs, DDR/PCI inputs, or internal logic (Figure 2). More details about the Cyclone clock network are available in the Cyclone II Device Family Data Sheet in the Cyclone II Device Handbook.