Nios II Processor Implementation in Cyclone II FPGAs

The Nios® II family of embedded processors, when implemented in Cyclone® II FPGAs, provides a cost-effective processing solution for both price-sensitive and compute-intensive applications. A Nios II embedded CPU core implemented in a Cyclone II device can achieve performance of over 100 DMIPs. With up to 68,416 LEs in the largest Cyclone II device, multiple instances of a Nios II core can be used within a single device, each of which can implement functions such as:

  • Running an operating system
  • Providing remote upgrades and FPGA configuration over an Ethernet connection
  • Data and I/O processing

Based on the successful first-generation Nios processor, a Nios II processor implemented in a Cyclone II FPGA offers an optimal way to address price-sensitive applications. The consumer, communications, computing, industrial, automotive, and wireless market segments can benefit from the integration of a soft embedded processor core into a low-cost FPGA. In particular, applications such as digital multimedia gateways, low-end switches and routers, and automotive infotainment systems, that benefit from a system-on-a-chip approach, can make use of Nios II processors and Cyclone II FPGAs.

Figure 1 shows how multiple Nios II embedded processors can be integrated into a Cyclone II device. In such a system it would be common to have a data movement processor controlling the flow of data between the external interfaces (PCI and Ethernet), the off-chip SDRAM, and any intellectual property cores. An additional processor could also be used to handle the man/machine interface (e.g., keypad, LCD display) to decouple this low-speed task from the higher-speed device functions.

Figure 1. System Implemented on Cyclone II FPGA

Notes:

  1. Input/output processor
  2. Man/machine interface processor

Nios II Family

The Nios II embedded processor family consists of three CPU cores: a high-performance core (Nios II /f, fast), a low-cost core (Nios II /e, economy), and a performance/cost balanced core (Nios II /s, standard). All three cores, available under a single royalty-free license, share a common 32-bit instruction set architecture (ISA) and are 100 percent binary code compatible. Figure 2 shows how these relate in size and performance.

Figure 2. Nios vs. Nios II Family Logic Use and Performance

Nios II processors can implement up to 256 custom instructions that allow critical software subroutines to be implemented in hardware, under operational control of the Nios II embedded processor. You can use custom instructions to implement functions that would take many clock cycles in software, but in hardware, complete in as little as one clock cycle, increasing system performance and data throughput. To increase the efficiency of these custom instructions even further, Cyclone II devices include M4K memory blocks for code and/or data storage and embedded 18x18 multipliers that can implement DSP functions.

The Nios II processor includes a library of peripherals that enable designers to turn a concept into a working design within minutes. These peripherals include:

  • Serial interfaces (UART, SPI, JTAG UART)
  • On-chip RAM and ROM, and interfaces to off-chip SRAM, flash, SSRAM, and SDRAM memories
  • General-purpose parallel I/O (GPIO)
  • Direct memory access
  • Joint Test Action Group (JTAG) debug interface

Complete Low-Cost SOPC Solution

Altera's SOPC Builder system development tool provides a powerful platform for composing systems on a programmable chip (SOPC) out of standard and user-creates IP functions, supporting over 60 peripherals from Altera and AMPPSM partners. With SOPC Builder, a Cyclone II designer can easily integrate components into a complete system, including processors, peripherals, on-chip memory and off-chip memory interfaces, and user-defined logic. SOPC Builder generates the Avalon® switch fabric in VHDL or Verilog HDL to connect the system, including multi-master bus arbitration and interrupt control logic. SOPC Builder also creates a simulation environment with a testbench for the custom hardware, as well as a software development environment with a library of C and assembly routines to access the peripherals in the custom system.

SOPC Builder can automatically connect any advanced high-performance bus master or slave peripheral, or any user-defined logic, via the simple Avalon bus interface. Refer to the Nios II peripherals & interfaces library for more details on the peripherals available for the Nios processor.