The Cyclone® II Device Handbook is comprised of the Cyclone II family data sheet along with detailed information on how to use Cyclone II features. Other topics include PCB layout guidelines, memory, configuration, and design considerations. To view the entire handbook, click the Cyclone II Device Handbook (All Sections) link below.
Get more information on Cyclone II Pin-Outs.
Section I. Cyclone II Device Family Data Sheet
Section II. Clock Management
Section III. Memory
Section IV. I/O Standards
Section V. Digital Signal Processing (DSP)
Section VI. Configuration & Testing
Section VII. PCB Layout Guidelines
Following are the most frequently asked questions about Cyclone® II devices.
System Clock Management
I/O Standards and Memory Interfaces
Software and Intellectual Property
Nios II Embedded Processors
The Cyclone II FPGA family is the second-generation family in our low-cost Cyclone series. Cyclone II FPGAs offer 30 percent lower cost and more than three times the logic density than first-generation Cyclone devices. Based on TSMC's proven 90-nm process technology with low-k dielectric, Cyclone II FPGAs are the lowest-cost FPGAs in the industry.
With densities ranging from 4,608 to 68,416 logic elements (LEs), Cyclone II FPGAs also offer new and enhanced features including up to 1.1 Mbits of embedded memory, up to 150 embedded 18 x 18 multipliers, phase-locked loops (PLLs), and support for external memory interfaces and differential and single-ended I/O standards.
The Cyclone II FPGA family is based on the 1.2-V, 90-nm, low-k dielectric process from TSMC, the same process technology used for Stratix II FPGAs.
The Cyclone II FPGA family is the optimum low-cost solution for high-volume applications in a wide variety of markets, including: consumer electronics, advanced communications and wireless, computer peripherals, industrial, and automotive. Selected Cyclone II FPGAs are available with industrial temperature or automotive- grade versions. Cyclone II FPGAs contain a number of new and enhanced features such as embedded memory, embedded multipliers, PLLs, and low-cost package offerings optimized for volume applications such as video displays, digital TVs (DTVs), digital set-top boxes (DSTBs), DVD players, DSL modems, residential gateways, and mid-range and low-end routers.
The Cyclone II family provides a flexible, risk-free option without up-front non-recurring engineering (NRE) charges or minimum order quantities. In addition to a cost structure unmatched by any other FPGA, Cyclone II FPGAs offer advanced features such as embedded 18 x 18 multipliers for high-performance digital signal processing (DSP) applications, and support for memory interfaces such as DDR2 (up to 334 Mbps) and QDRII (up to 688 Mbps).
The Cyclone II FPGA family includes six members ranging in density from 4,608 to 68,416 LEs. Low-cost packages with vertical migration support are available for Cyclone II FPGAs, including the thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine BGA packages. Table 1 provides an overview of the Cyclone II family, and Table 2 lists the package options and user I/O pins.
|Logic Elements (LEs)||4,608||8,256||18,752||33,216||50,528||68,416|
|M4K RAM Blocks||26||36||52||105||129||250|
|Total RAM Bits||119,808||165,888||239,616||483,840||594,432||1,152,000|
|Embedded 18x18 Multipliers||13||18||26||35||86||150|
|Maximum User I/O Pins||142||182||315||475||450||622|
Ultra FineLine BGA
Cyclone II FPGAs offer lower prices and higher densities than the first-generation Cyclone FPGAs. Cyclone II FPGAs are built on 90-nm process technology, while the Cyclone family uses 0.13 µm. The second-generation devices also offer more features such as: embedded multipliers, more PLLS, support for more I/O standards, and interface to newer memory devices.
The Cyclone II and Stratix® II FPGA families were built to address different market needs. The basic building block for the Stratix II FPGA family is the adaptive logic module (ALM), while Cyclone II FPGAs use LEs consisting of 4-input look-up tables (LUT) and registers as the basic building blocks. However, Cyclone II FPGAs share some similarities with Stratix II FPGAs, such as:
The density overlap between the two families exists because of the need to address different market requirements. Stratix II FPGAs are high-performance and high-density FPGAs with robust features for high-end applications. As the industry's lowest-cost FPGAs, Cyclone II FPGAs aptly include features and capabilities that target high-volume applications where cost is the most critical factor.
No, Cyclone II FPGAs are not pin-compatible with Cyclone FPGAs. Cyclone II design goals prioritized low cost as the primary objective. Pin compatibility between families adds undesirable die size.
Unlike competing FPGAs that require three power supplies, Cyclone II FPGAs simplify power management in a system by requiring only two: one for VCCINT (1.2 V) and one for VCCIO (3.3 V, 2.5 V, 1.8 V, or 1.5 V) that is user-controllable.
Cyclone II FPGAs offer up to 150 embedded 18 x 18 multipliers capable of running at 250 MHz. The embedded multipliers can also be configured as two 9 x 9 multipliers, offering up to 300 9x9 multipliers. These multipliers are capable of efficiently implementing multiplication operations commonly found in digital signal processing (DSP) applications. Embedded multipliers in Cyclone II FPGAs can boost overall system performance and decrease system costs for cost-sensitive DSP applications.
The Cyclone II embedded memory consists of columns of 4-Kbit M4K RAM blocks, each capable of data transfer rates of over 250 MHz. Each M4K RAM block can implement various types of memory, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Each block also includes extra parity bits for error control, mixed-width mode, and mixed-clock mode support.
Cyclone II FPGAs provide a global clock network and PLLs with on- and off-chip capabilities for a complete system clock management solution. Cyclone II FPGAs have up to sixteen dedicated clock input pins that feed the global clock network lines directly.
The global clock network in Cyclone II FPGAs consists of sixteen global clock lines accessible throughout the entire device. It is optimized to minimize skew, providing clock, clear, and reset signals to all resources within the device.
Cyclone II FPGAs offer up to four PLLs. These PLLs provide general-purpose clocking management capabilities such as multiplication and phase shifting, programmable duty cycle, programmable bandwidth, spread spectrum input clocking, lock detection, as well as outputs for differential I/O pin support. The external clock outputs (one per PLL) can be used to provide clocks to other devices in the system, eliminating the need for other clock-management devices on the board.
Cyclone II FPGAs support dedicated, speed-optimized circuitry to interface with single data rate (SDR), double data rate (DDR) and DDR2 SDRAM devices and QDRII SRAM devices. Table 3 shows the clock speed and maximum data transfer rate for each memory interface.
|Memory Device Type||Maximum Clock Speed||Maximum Data Transfer Rate|
|SDR SDRAM||167 MHz||167 Mbps|
|DDR SDRAM||167 MHz||334 Mbps|
|DDR2 SDRAM||167 MHz||334 Mbps|
|QDRII SRAM||167 MHz||668 Mbps|
Cyclone II FPGAs support a variety of single-ended I/O standards, including LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X. Single-ended I/O standards provide more current drive capacity than differential I/O standards, and they are critical when working with advanced memory devices such as DDR and DDR2 SDRAM devices. Cyclone II devices also support a programmable drive strength control for certain I/O standards with settings ranging from 2 mA up to 24 mA. Table 4 lists the single-ended I/O standards supported in Cyclone II devices and their respective performance.
|I/O Standard||Performance||Typical Application|
|3.3-V/2.5-V/1.8-V LVTTL||167 MHz||General Purpose|
|3.3-V/2.5-V/1.8-V/1.5-V LVCMOS||167 MHz||General Purpose|
|3.3-V PCI||66 MHz||PC and Embedded|
|3.3-V PCI-X||100 MHz||PC and Embedded|
|2.5-V/1.8-V SSTL Class I||167 MHz||Memory|
|2.5-V/1.8-V SSTL Class II||133/125 MHz||Memory|
|1.8-V/1.5-V HSTL Class I||167 MHz||Memory|
|1.8-V/1.5-V HSTL Class II||100 MHz||Memory|
Cyclone II FPGAs provide support for LVDS, mini-LVDS, RSDS, and LVPECL. LVDS performance is 622 Mbps for transmit data and 805 Mbps for receive data. On the transmission side, Cyclone II FPGAs require an external resistor network to convert the output to the appropriate LVDS swing levels. Table 5 lists the differential I/O standards supported by the Cyclone II FPGA family:
|I/O Standard||Performance||Typical Application|
|Differential HSTL||167 MHz||Memory|
|Differential SSTL||167 MHz||Memory|
|LVDS||805 Mbps (receiver), 622 Mbps (transmitter)||Chip-to-Chip Backplane Driver|
The Quartus II subscription software and the free Quartus II Web Edition software version 4.1 and later offer design capability for Cyclone II FPGAs.
Synthesis and simulation tools from leading EDA vendors (Cadence, Mentor Graphics®, Synopsys, and Synplicity) support the Cyclone II device family, ensuring the highest quality of results in our devices. These tools include:
More than 40 intellectual property (IP) cores are optimized for Cyclone II FPGAs. Various IP cores from us and our partners are specifically optimized for the Cyclone II FPGA architecture, including:
To offer the lowest total solution cost, we created a low-cost serial configuration device family for Cyclone II FPGAs. On average, these serial configuration devices are priced for volume applications as low as 10 percent of the price of the corresponding Cyclone II FPGA. Four serial configuration devices (1-Mbit, 4-Mbit, 16-Mbit, and 64-Mbit) are offered in space-saving 8-pin and 16-pin small-outline integrated circuit (SOIC) packages.
Yes, Cyclone II FPGAs support Nios II embedded processors, our obsolescence-free, user-configurable general-purpose RISC soft embedded processor family. Second-generation Nios II processors extend our soft embedded processor leadership with better performance, lower cost, and the most complete set of software development tools available anywhere. The Cyclone II FPGA family can incorporate multiple Nios II processors in one device, providing savings in cost, footprint, and power efficiency. Cyclone II FPGAs provide designers with maximum flexibility, balance performance needs, and device resource usage by supporting three distinct Nios II cores, each optimized for a particular price and performance range. All three cores support a single instruction set architecture, making them 100 percent code-compatible.