Cyclone III Architecture

The Cyclone III architecture consists of up to 120K vertically arranged logic elements (LEs), 4 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, and 200 18x18 embedded multipliers. Cyclone III LS FPGAs have a memory-rich and multiplier-rich floorplan consisting of up to 200K logic elements, 8.2 Mbits of embedded memory, and 396 embedded multipliers.

Both architectures include highly efficient interconnect and low-skew clock networks, providing connectivity between logic structures for clock and data signals. The logic and routing core fabric is surrounded by I/O elements (IOEs) and phase-locked loops (PLLs).

The low-power Cyclone® III FPGA family is the third generation in the Altera® Cyclone FPGA series. With its unprecedented combination of low power, high functionality, and low cost, the Cyclone III FPGA family broadens the number of high-volume, cost-sensitive applications that can benefit from an FPGA. The Cyclone III LS variant extends the family with higher density, higher memory, smaller packages, and security features to protect your intellectual property (IP).

Tables 1 and 2 provide overviews of device features for Cyclone III and Cyclone III LS FPGAs, while Table 3 provides device package and maximum user I/O information for the FPGA family. You'll find device speed grades in Table 4 and industrial temperature support data in Table 5.

Table 1. Cyclone III FPGA Family Overview

Device EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120
Logic elements (LEs)5,13610,32015,40824,62439,60055,85681,264119,088
M9K embedded memory blocks (1)46465666126260305432
Embedded memory (Kbits)4144145045941,1342,3402,7453,888
18-bit x 18-bit embedded multipliers23235666126156244288
Phase-locked loops (PLLs)22444444
Maximum user I/O pins182182346215535377429531
Differential channels707014083227163181233
AvailabilityBuy NowBuy NowBuy NowBuy NowBuy NowBuy NowBuy NowBuy
Now

Table 2. Cyclone III LS FPGA Variant Overview

Device EP3CLS70 EP3CLS100 EP3CLS150 EP3CLS200
LEs70,208100,448150,848198,464
M9K embedded memory blocks (1)333483666891
Embedded memory (Kbits)2,9974,3475,9948,019

18-bit x 18-bit embedded multipliers
200267320396
PLLs4444
Maximum user I/O pins413413413413
Differential channels113113181181

Note:

  1. M9K memory blocks offer 9,216 bits per block (including parity bits).

Table 3. Cyclone III Device Packages and Maximum User I/Os (1)

Device/Package
(mm x mm)

144-Pin
EQFP
(22 x 22)
(2)

164-Pin
MBGA
(8 x 8)
(7)
240-Pin
PQFP
(32 x 32)
(3)

256-Pin FBGA
(17 x 17)
(4)

256-Pin UBGA
(14 x 14) (5)

324-Pin FBGA
(19 x 19)

484-Pin FBGA
(23 x 23)

484-Pin UBGA
(19 x 19)

780-Pin FBGA
(29 x 29)

EP3C5

94

106   182 182        
EP3C10

94

106   182 182        
EP3C16

84

92 160 168 168   346 346  
EP3C25

82

  148 156 156 215      
EP3C40

 

  128     196 331 331 535 (6)
EP3C55

 

          327 327 377
EP3C80

 

          295 295 429
EP3C120

 

 

 

 

 

 

283

 

531

EP3CLS70

 

 

 

 

 

 

278

278

413

EP3CLS100

 

 

 

 

 

 

278

278

413

EP3CLS150

 

 

 

 

 

 

210

 

413

EP3CLS200

 

          210   413
Notes:
  1. Color denotes vertical migration
  2. EQFP = Enhanced thin quad flat pack
  3. PQFP = Plastic quad flat pack
  4. FBGA = FineLine BGA (1.0-mm pitch)
  5. UBGA = Ultra FineLine BGA (0.8-mm pitch)
  6. EP3C40 in the F780 package supports restricted vertical migration
  7. MBGA = Micro BGA (0.5-mm pitch)

Table 4. Cyclone III FPGA Family Speed Grades (1), (2)

Device 144-Pin EQFP 164-Pin MBGA 240-Pin PQFP 256-Pin FBGA 256-Pin UBGA 324-Pin FBGA 484-Pin FBGA 484-Pin UBGA 780-Pin FBGA
EP3C5 -7, -8 -7, -8   -6, -7,
-8
-6, -7,
-8
       
EP3C10 -7, -8 -7, -8   -6, -7,
-8
-6, -7,
-8
       
EP3C16 -7, -8 -7, -8 -8 -6, -7,
-8
-6, -7,
-8
  -6, -7,
-8
-6, -7,
-8
 
EP3C25 -7, -8   -8 -6, -7,
-8
-6, -7,
-8
-6, -7,
-8
     
EP3C40     -8     -6, -7,
-8
-6, -7,
-8
-6, -7,
-8
-6, -7,
-8
EP3C55             -6, -7,
-8
-6, -7,
-8
-6, -7,
-8
EP3C80             -6, -7,
-8
-6, -7,
-8
-6, -7,
-8
EP3C120

 

 

 

 

 

 

-7, -8

 

-7, -8

EP3CLS70

 

 

 

 

 

 

-7, -8

-7, -8

-7, -8

EP3CLS100

 

 

 

 

 

 

-7, -8

-7, -8

-7, -8

EP3CLS150

 

 

 

 

 

 

-7, -8

 

-7, -8

EP3CLS200

 

 

 

 

 

 

-7, -8

 

-7, -8

Notes:

  1. Cyclone III FPGAs are available in up to three speed grades, with -6 being the fastest.
  2. For Cyclone III devices, Altera's guideline for core fMAX change between each speed grade is on average 15 to 20 percent.

Table 5. Cyclone III Device Industrial Temperature Support

Device

Package

Speed Grade

EP3C5

144-pin EQFP
164-pin MBGA
256-pin FBGA
256-pin UBGA

-7
EP3C10144-pin EQFP
164-pin MBGA
256-pin FBGA
256-pin UBGA
-7
EP3C16144-pin EQFP
164-pin MBGA
256-pin FBGA
256-pin UBGA
484-pin FBGA
484-pin UBGA
-7
EP3C25144-pin EQFP
256-pin FBGA
256-pin UBGA
324-pin FBGA
-7
EP3C40324-pin FBGA
484-pin FBGA
484-pin UBGA
780-pin FBGA
-7
EP3C55484-pin FBGA
484-pin UBGA
780-pin FBGA
-7
EP3C80484-pin FBGA
484-pin UBGA
780-pin FBGA
-7
EP3C120

484-pin FBGA
780-pin FBGA

-7

EP3CLS70

484-pin FBGA
484-pin UBGA
780-pin FBGA

-7

EP3CLS100

484-pin FBGA
484-pin UBGA
780-pin FBGA

-7

EP3CLS150

484-pin FBGA
780-pin FBGA

-7

EP3CLS200484-pin FBGA
780-pin FBGA
-7

Notes:

  1. Cyclone III FPGAs are available in up to three temperature grades to support varying operating environments with junction temperature support from -40°C to 125°C.
  2. The Cyclone III LS variant is available in two temperature grades with junction temperature support from -40°C to 100°C.