As your FPGA design grows larger, good clock management becomes essential. Cyclone® III FPGAs include an extensive global clocking structure and fully featured robust phase-locked loops (PLLs). The larger Cyclone III FPGAs feature up to 20 global clocks that can also be used as global signals. The clock system can also be powered down when not in use to save power.
Cyclone III FPGAs have up to four enhanced PLLs that provide advanced clock management capabilities such as dynamic reconfiguration, cascadability, programmable phase shift, external clock output, programmable duty cycle, lock detection, spread-spectrum input clocking, and high-speed differential support on the input and output clocks. The PLLs in Cyclone III FPGAs simplify timing issues and overall board layout. Cyclone III FPGA PLLs provide cost-efficient timing control for applications including consumer, communications, computing, automotive, industrial, and wireless systems. Figure 1 shows a block diagram of Cyclone III FPGA PLLs.
Table 1 lists the PLL features of Cyclone III FPGAs
Table 1. PLL Features of Cyclone III FPGAs
|Clock Multiplication and Division||m/(n x post-scale counter)|
|Phase Shift||Resolution down to 96-ps increments|
|Programmable Duty Cycle||Supported|
|Spread Spectrum||Supported on input clocks|
|Automatic Clock Switchover||Yes|
|Number of Internal Clock Outputs||5|
|Number of External Clock Outputs||Up to one differential or one single-ended|
|I/O Standard Support on Input Clock and External Clock Output||LVTTL, LVCMOS, 2.5/1.8/1.5 V, PCI, SSTL, LVDS, HSTL, PCI-X, LVPECL|
A new feature in Cyclone III FPGAs allows you to reconfigure the PLL in real time, which is useful in applications that operate at multiple frequencies. It can also be used in prototype and test environments, allowing you to sweep PLL output frequencies and adjust the output-clock phase dynamically. The pre-scale counter, feedback counter, post-scale counters, post voltage-controlled oscillator (VCO) divider, and other parameters are some of the components that are reconfigurable, allowing you to adjust both frequency and phase.
Another new feature in Cyclone III FPGAs allows you to cascade two PLLs together. This allows you to generate up to 10 internal and 2 external clocks from one clock source. It also provides more and finer clock frequency possibilities.
Cyclone III FPGAs support automatic clock switchover in addition to manual clock switchover. The circuitry automatically detects if the reference clock is present and, if not, switches over to the redundant clock.
PLLs in Cyclone III FPGAs provide a clock synthesis capability that allows the internal clocks to operate at a different frequency than the input clock frequency. Each PLL can provide up to five clock outputs that can operate at different frequencies. The PLLs offer a frequency multiplication by m or division by (n x post-scale counter) scaling factor, where m, n, and the post-scale counter can be any integer from 1 to 512.
Cyclone III FPGA PLLs allow you to implement time-domain multiplexed applications where a given circuit is used more than once per clock cycle. By using time-domain multiplexing, you can implement a given function with fewer logic cells, thereby improving device area efficiency by sharing resources within the device.
Each PLL supports one differential or one single-ended external output clock. There is one external clock output pin pair per PLL. The external clock output pins support various I/O standards, as shown in Table 1. You can use the external clock output for system clocking or for synchronizing different devices on the board. The clock feedback feature can compensate for internal delay or can phase-align the external clock output with the clock input.
Cyclone III PLLs have advanced clock-shift capability to enable programmable phase shifts. You can perform phase shifting in time units with a resolution down to 96 picoseconds (ps). The programmable phase-shift feature is ideal for meeting timing constraints such as set-up and hold times where the exact location of the clock edge is critical.
The lock output indicates that there is a stable clock output signal in phase with the reference clock. You can use the lock detect signal for system control and synchronization of different devices on the board.
The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. The programmable duty cycle feature is useful in DDR applications where the data is transferred on both the positive and the negative edge of the clock. Programmable duty cycle allows you to manipulate the position of the positive and negative edges of the clock, which simplifies the set-up and hold-time requirements associated with these edges.
Spread-spectrum technology reduces electromagnetic interference (EMI) in a system. This technology works by distributing the clock energy over a broad frequency range. Cyclone III FPGAs can accept a spread-spectrum input with typical modulation frequencies.