Cyclone V FPGAs: 40% Lower Power

Cyclone V Power Consumption Compared to Previous-Generation FPGAs

Silicon and Architectural Optimizations

Altera has taken significant steps to reduce power in Cyclone V FPGAs including use of the 28-nm LP process technology, reduced core voltage, diligent selection of low VT and high VT transistors to reduce static power, lower gate capacitance, power-optimized transceiver architecture, and an increased amount of hardened intellectual property (IP). For example, the new multiport memory controller hard IP block and the PCI Express® hard IP block consume less than 10 percent and 20 percent of their soft logic implementations, respectively. These blocks along with transceiver blocks can be shut down if unused, thus providing a mechanism to further lower your design's total power consumption.

Benefits of Low Power Consumption

The combination of increased integration and a low-power Cyclone V FPGA results in significant system-level benefits for a variety of applications:

  • Portable or handheld battery-powered devices
  • Space-constrained and other thermally challenging environments
  • Price-sensitive applications where cooling systems are not cost effective

Accurate Power Estimation and Analysis

Altera makes power estimation and analysis from design concept through implementation easy, with the most accurate and complete power management design tools in the industry. Altera offers the following power estimation and analysis resources:

When designing, you can use the PowerPlay early power estimator (EPE) during the design concept phase and the PowerPlay power analyzer during the design implementation phase. The PowerPlay EPE is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization. The power models in the PowerPlay EPE are correlated to silicon, ensuring an accurate estimation of your design's power consumption.

The PowerPlay power analyzer is a far more detailed power analysis tool that uses actual design placement and routing, logic configuration, and simulated waveforms to estimate dynamic power very accurately. The power analyzer, in aggregate, provides approximately 10-percent accuracy when used with accurate design information. Quartus Prime PowerPlay power models are correlated to silicon measurements based on over 5,000 test configurations per circuit.

Throughout the design process the Power Management Resource Center provides useful information regarding power, thermal management, and power supply management .

Quartus Prime Power Optimization

Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area tradeoffs have been automated within the register transfer level (RTL) through the place-and-route design flow. Altera has taken a leadership position in bringing power optimization into the design flow. Quartus Prime PowerPlay optimization tools automatically use the Cyclone V architecture capabilities to reduce power further, resulting in up to 10 percent lower total power consumption when enabled.

The Quartus Prime software has many automatic power optimizations that are transparent to you but provide optimal utilization of FPGA architecture details to minimize power, including:

  • Transforming major functional blocks
  • Mapping user RAM so they use less power
  • Restructuring logic to reduce dynamic power
  • Correctly selecting logic inputs to minimize capacitance on high-toggling nets
  • Reducing area and wiring demand for core logic to minimize dynamic power in routing
  • Modifying placement to reduce clocking power