Altera's Cyclone® V FPGAs provide the industry's lowest system cost and power, along with performance levels that make the device family ideal for differentiating your high-volume applications. You'll get up to 40 percent lower total power compared with the previous generation, efficient logic integration capabilities, integrated transceiver variants, and SoC FPGA variants with an ARM®-based hard processor system (HPS).
Purchase the Cyclone V GX Starter Kit for only $179!
Cyclone V Variants
|Features||Lowest cost and power||3.125G transceivers||6.144G transceivers|
|Optimized for lowest system cost and power for a wide spectrum of general logic and DSP applications||Optimized for lowest cost and power for 614 Mbps to 3.125 Gbps transceiver applications||FPGA industry’s lowest cost and power for 6.144 Gbps transceiver applications(1)|
|FPGA||E Variant||GX Variant||GT Variant|
|Integrated ARM CortexTM-A9 MPCoreTM Processor System||SE Variant||SX Variant||ST Variant|
Cyclone V GT devices support 6.144 Gbps CPRI protocol.
Tailored for High-Volume, Cost-Sensitive Applications
With Cyclone V FPGAs, you can get the power, cost, and performance levels you need for high-volume applications including protocol bridging, motor control drives, broadcast video converter and capture cards, and handheld devices. Learn more about the advantages of Cyclone V FPGAs in a variety of market segments.
SoC FPGAs – Your Customizable ARM Processor-Based SoC
SoC FPGAs let you reduce system power, system cost, and board space by integrating a HPS – consisting of processors, peripherals, and memory controller – with the FPGA fabric using a high-bandwidth interconnect backbone. The combination of the HPS with Altera's 28 nm low-power FPGA fabric provide the performance and ecosystem of an applications-class ARM processor with the flexibility, low cost, and low power consumption of the Cyclone V FPGAs.
Reducing Total System Cost Through Integration
Because Cyclone V FPGAs integrate an abundance of hard intellectual property (IP) blocks, you can differentiate and do more with less overall system cost, power, and design time. Key hard IP blocks include the following:
- Hard memory controllers supporting 400 MHz DDR3 SDRAM with optional error correction code (ECC) support
- PCI Express® (PCIe®) Gen2 with multifunction support
- Variable-precision digital signal processing (DSP) blocks
- HPS Dual-core ARM Cortex-A9 MPCore processor
The devices are built on TSMC's 28 nm Low-Power (28LP) process, which brings down the power and cost required by cost-sensitive applications.
- Up to 40 percent lower total power compared with Cyclone IV GX FPGAs
- Lowest power serial transceivers with 88 mW maximum power consumption per channel at 5 Gbps
- Over 4,000 MIPS (Dhrystones 2.1 benchmark) processing performance for under 1.8 W (for SoC FPGA)
- Lower power due to increased use of hard IP blocks
Also lowering cost – the FPGAs require only two power regulator voltages and come in wire-bond packages with small form factor options.