Industry's Most Cost-Effective Programmable Architecture

Altera's Cyclone™ family of FPGAs provides the benefits of programmable logic at price points that are competitive with ASICs and ASSPs. These low-cost devices are built from the ground up based on extensive input from hundreds of customers and provide high-volume application-focused features such as embedded memory, external memory interfaces, and clock management circuitry.

Altera broke new ground with the Cyclone FPGA family, the first generation of the Cyclone series. The Cyclone device family, the FPGA performance leader, is based on a low-cost architecture, built from the start with cost savings in mind. Cyclone devices enable the development of new, programmable solutions in price-sensitive applications where FPGAs were once considered too expensive. They offered a new low-cost alternative for applications currently using application-specific integrated circuits (ASICs) that risk significant non-recurring engineering (NRE) charges, prolonged delivery to market, and design re-spins. With unmatched price points, features, and performance, Cyclone devices are the low-cost FPGA family designers had been waiting for, as seen by the huge demand for these devices with milions of units having been bought by thousands of unique customers worldwide.

Designers needing lower costs, more density and functionality for high-volume applications can take advantage of Cyclone II FPGAs.

Challenges of Cost-Optimization

Programmable logic suppliers have many challenges when designing cost-reduced FPGAs. The most significant challenge is addressing the tradeoff between performance, features, and overall device cost. FPGA designers must strike a delicate balance (Figure 1) to ensure sufficient logic and memory density for system-on-a-programmable-chip (SOPC) solutions while providing adequate performance at reasonable prices.

Figure 1. Balancing Device Performance, Features & Cost

Getting Much More for Much Less

The first step in developing a programmable logic device (PLD) that satisfies the requirements for volume-driven applications is adopting new design methods. Part of the new methodology Altera adopted was to bring in existing and potential customers into the product-definition process. These customers identified the threshold price points, key features, and performance required to make FPGAs a viable solution in high-volume systems.

Cyclone devices are built starting with carefully selected small form-factor packages that offer the user-sufficient I/O pins and power dissipation characteristics. The maximum size of a pad-limited die can be determined from the physical dimensions of the package. The device is then populated with as many logic structures and memory blocks as possible, guaranteeing the most functionality in the available area within each package.

In addition, Altera achieved several design and process efficiencies for a further die size reduction, which directly translate into overall cost savings for the FPGA user.

A sound approach to low-cost design coupled with area-saving innovations yield Cyclone devices—the industry's only truly cost-optimized product. Cyclone II FPGAs are apporpriate for designers needing lower costs, more density, and functionality for high-volume applications.

Cyclone Architecture

Abundant logic and memory resources, clock management circuitry, and advanced I/O capabilities are all available in Cyclone devices.

The Cyclone architecture consists of vertically arranged logic elements (LEs), embedded memory blocks, and phase-locked loops (PLLs) that are surrounded by I/O elements (IOEs) (Figure 2). A highly efficient interconnect and low-skew clock network provide connectivity between each of these structures for clock and data signals.

Figure 2. EP1C20 Device Floorplan

Area-efficient IOEs are grouped into I/O banks around the device, offering significant capabilities while consuming minimal die area. They include support for a range of single-ended and differential I/O standards, such as SSTL-2, SSTL-3, and the LVDS I/O standard at up to 640 megabits per second (Mbps). Each IOE contains three registers for implementing double data rate (DDR) applications and associated circuitry for other I/O features like programmable drive strength, bus hold, and programmable slew rate.

The I/O banks are equipped with dedicated external memory interface circuitry. This circuitry simplifies data transfer with external memory devices, including DDR SDRAM and FCRAM devices. Maximum data transfer rates reach speeds of up to 266 Mbps (133-MHz clock).

Cyclone devices are 32-bit/66-MHz PCI compliant. Each IOE provides multiple paths from the pin to the core, allowing the device to meet associated set-up and hold times.

Cyclone devices range in density from 2,910 LEs and 59,904 bits of RAM to 20,060 LEs and 294,912 bits of RAM. More information is available on the Cyclone overview page.

Clock Distribution

Each Cyclone device is served by a global clock network composed of up to eight distinct clock lines. These clock lines are accessible from anywhere in the device and can be fed either by input pins, PLL outputs, DDR/PCI inputs, or internal logic (Figure 3). More details about the Cyclone clock network are available in the Cyclone Device Family Data Sheet in the Cyclone Device Handbook.

Figure 3. Cyclone Device Clock Network

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