Cyclone Devices & Nios II Embedded Processors

The Nios® II family of embedded processors implemented in Cyclone™ devices offers a cost-effective soft processor solution for cost-sensitive processing applications. Consuming fewer than 600 logic elements (LEs), a Nios II processor in a low-cost Cyclone device delivers an extremely economical solution—one that is less expensive than most discrete 32-bit microcontrollers available today.

With up to 20,060 LEs available in the largest Cyclone device, multiple Nios II processors can easily fit into one Cyclone device. Low-cost Nios II processors are perfectly suited for a wide range of cost-sensitive consumer, communications, computing, industrial, automotive, and wireless end-applications. Designers can now use the low-cost SOPC solution provided by the Nios II family of embedded processors in Cyclone devices for applications such as digital entertainment boxes, low-end routers and switches, industrial motor and servo controllers, and automotive telematics.

The Nios II family of embedded processors is based on the extremely successful first-generation Nios processors and delivers three processor cores to address an even wider range of embedded processing applications. Designers can choose from a high-performance core (over 200 DMIPS), a low-cost core (as little as 35 cents in logic), and a performance-/cost-balanced standard core. The Nios II family of processors addresses applications such as:

Figure 1 shows an example of how a Nios II embedded processor can be used in a Cyclone device. A full-featured, performance-optimized Nios II processor core with peripherals can be tailored for the specific requirements of virtually any embedded system. With a Nios II processor in a Cyclone device, a 32-bit, 20-DMIPS RISC processor now costs as little as 35 cents. The device can quickly and easily perform updates without incurring additional costs, and it will stave off obsolescence and extend usability beyond that of many off-the-shelf microprocessors and microcontrollers.

Figure 1. Cost-Effective Nios II Embedded Processor Solution

Notes to Figure 1:

  1. Cyclone EP1C20F324 device information:
    • Density: 20,060 LEs
    • Package: 324-pin FineLine BGA®
    • Price: US $18.00 (based on pricing for 250K units in Q4 2004)
  2. Nios II processor and peripherals use about 600 LEs.

Developers can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Custom instructions implement complex processing tasks in hardware in as few as one clock cycle, which provides a cost-effective method for system optimization. User-added custom instruction logic can access memory and logic outside the Nios II system, allowing extremely efficient and flexible access to data and logic resources. This gives designers the flexibility and portability of high-level software design, while maintaining the performance benefits of parallel hardware operations in programmable logic devices (PLDs).

Complete Low-Cost SOPC Solution

Altera's Qsys system integration tool provides designers with a powerful platform for composing bus-based systems from common system components. With Qsys, a Cyclone designer can easily integrate components into a complete system that includes processors, peripherals, on-chip memory and off-chip memory interfaces, and user-defined logic. Qsys generates the VHDL or Verilog HDL code to connect the system, including multi-master bus arbitration, and interrupt control logic. Qsys also creates a simulation environment with a testbench for the custom hardware, and can be used to launch the Nios II integrated development environment (IDE).

Designers can use the Qsys library of customizable peripherals to turn a concept into a working system within minutes. These peripherals include:

  • Serial interfaces, such as UART and serial peripheral interface (SPI)
  • On-chip RAM and interfaces to off-chip SRAM, flash, SSRAM, and SDRAM memories
  • General-purpose parallel I/O blocks
  • Direct memory access (DMA)
  • Joint Test Action Group (JTAG) debug interface

The Nios II IDE is a complete software development environment that handles all software development tasks, such as program editing, compiling, and debugging.

Nios II processor users can take advantage of a memory interface to low-cost single data rate (SDR) SDRAM, which is accessible through a tri-state bridge to conserve I/O pins. Nios II processor users targeting Cyclone devices can also utilize unused memory capacity in serial configuration devices. The Nios II development kits include a memory interface and software routines to use this available memory space for general-purpose system memory, which can be used for code and data storage, saving in memory costs. System designers can also save I/O pins and reduce component costs and board space by using the JTAG interface for configuration, hardware debug, software debug, and terminal communication.

Qsys can automatically connect any advanced high-performance bus (AHB) master or slave peripheral or any user-defined logic via the simple Avalon™ switch fabric. The Nios II Peripherals and Interfaces web page gives more details on the peripherals available for Nios II processors.

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