Cyclone V SoC Hard Processor System

Cyclone SoC Block Diagram

HPS Features

  • 925 MHz, dual-core ARM® Cortex™-A9 MPCore™ processor
  • Each processor core includes:
    • 32 KB of L1 instruction cache, 32 KB of L1 data cache
    • Single- and double-precision floating-point unit and NEONTM media engine
    • CoreSightTM debug and trace technology
  • 512 KB of shared L2 cache
  • 64 KB of scratch RAM
  • Multiport SDRAM controller with support for DDR2, DDR3, and LPDDR2 and optional error correction code (ECC) support
  • 8-channel direct memory access (DMA) controller
  • QSPI flash controller
  • NAND flash controller with DMA
  • SD/SDIO/MMC controller with DMA
  • 2x 10/100/1000 Ethernet media access control (MAC) with DMA
  • 2x USB On-The-Go (OTG) controller with DMA
  • 4x I2C controller
  • 2x UART
  • 2x serial peripheral interface (SPI) master peripherals, 2x SPI slave peripherals
  • Up to 134 general-purpose I/O (GPIO)
  • 7x general-purpose timers
  • 4x watchdog timers

High-Bandwidth HPS-to-FPGA Interconnect Backbone

Although the HPS and the FPGA can operate independently, they are tightly coupled via a high-bandwidth system interconnect built from high-performance ARM AMBA® AXITM bus bridges. IP bus masters in the FPGA fabric have access to HPS bus slaves via the FPGA-to-HPS interconnect. Similarly, HPS bus masters have access to bus slaves in the FPGA fabric via the HPS-to-FPGA bridge. Both bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. Up to six FPGA masters can share the HPS SDRAM controller with the processor. Additionally, the processor can be used to configure the FPGA fabric under program control via a dedicated 32 bit configuration port.

  • HPS-to-FPGA: configurable 32, 64, or 128 bit AMBA AXI interface
  • FPGA-to-HPS: configurable 32, 64, or 128 bit AMBA AXI interface
  • FPGA-to-HPS SDRAM controller: up to 6 masters (command ports), 4x 64 bit read data ports and 4x 64 bit write data ports
  • 32 bit FPGA configuration manager