To meet demands for higher precision signal processing, we have developed the industry's first variable-precision digital signal processing (DSP) block. This integrated block, part of the Stratix® V, Arria® V, and Cyclone® V FPGA 28-nm DSP Portfolio, allows each block to be configured at compile time into an 18-bit mode or in a high-precision mode.
With the variable-precision DSP block, the Arria V and Cyclone V FPGAs support, on a block-by-block basis, various precisions ranging from 9-bit x 9-bit up to single-precision floating point (mantissa multiplication) within a single DSP block. This frees you from FPGA architecture restrictions, allowing you to use the optimum precision at each stage of the DSP datapath. You'll also benefit from increased system performance, reduced power consumption, and reduced architectural constraints.
Webcast: Enabling High-Performance DSP with Arria V or Cyclone V Variable-Precision DSP Block
This webcast describes the five key enhancements in the DSP block of the Arria V and Cyclone V FPGAs. The DSP block features the variable-precision architecture which allows you to choose the desired precision for each block.
The variable-precision DSP block in Arria V and Cyclone V FPGAs are optimized to provide the following enhancements:
- 108 inputs, 74 outputs
- 18x19 multiply mode, allowing the pre-adder to use two 18-bit inputs
- Optional second accumulator (feedback register) for complex serial filtering
- Dual 18x19 independent multipliers
- No restriction on use of hard pre-adder and external coefficients in 18-bit mode
Figure 1. Arria V and Cyclone V FPGA Variable-Precision DSP Block Architecture, 18-Bit Precision Mode
Figure 2. Arria V and Cyclone V FPGA Variable-Precision DSP Block Architecture, High-Precision Mode
Arria V and Cyclone V FPGA Multiplier Precision Range in Single- and Multiple-Block Modes
|Table 1. Arria V and Cyclone V FPGA Multipliers in Single-Block Mode|
|Number of Multipliers||
|Three independent multipliers||
|Two multipliers in sum mode||
|Two independent multipliers||
|One independent asymmetric multiplier||
|One independent high-precision multiplier||
|Table 2. Arria V and Cyclone V FPGA Multipliers in Multiple-Block Mode|
|Type of Multipliers||
Number of Blocks Required
|One independent 36x36 multiplier||
|One independent 54x54 multiplier||
|One 18x18 complex multiplier||
|One 18x25 complex multiplier||
|One 18x36 complex multiplier||
|One 27x27 complex multiplier||
1. Requires additional logic outside the DSP block
All modes feature a 64-bit accumulator and each variable-precision DSP block comes with a 64-bit cascade bus that allows implementation of even higher precision signal processing by cascading multiple blocks using a dedicated bus.
The variable-precision DSP architecture maintains backward compatibility. It can efficiently support existing 18-bit DSP applications, such as high-definition video processing, digital up or down conversion, and multi-rate filtering.
Applications for Arria V or Cyclone V FPGAs
- Industrial video
- Broadcast systems
- Wireless systems
- Medical imaging
- Military radar
- High-performance computing