The architectural innovation in the implementation of IEEE 754 single-precision hardened floating-point DSP (digital signal processing) blocks in Arria® 10 FPGAs and SoCs enable processing rates up to 1.5 TFLOPs (Tera Floating-point Operations Per Second) and power efficiency up to 40 GFLOPs/Watt.
With the three modes available for Arria® 10 DSP blocks: standard-precision fixed-point, high-precision fixed point and single-precision floating-point, designers can implement a variety of algorithms that require fixed point all the way to double-precision IEEE 754 compliant floating-point operations. Hardened floating-point processing offers designers the ability to implement algorithms in floating point with the similar performance and power efficiency as fixed point. This can be achieved without any power, area, or density compromises and with no loss of fixed-point features or functionality.
Arria 10 FPGAs and SoCs are a compelling solution for industrial, wireless systems, compute intensive applications such as high performance computing, machine learning, high-precision radars and data center acceleration applications.
Learn more about the floating-point processing capabilities for Arria 10 FPGAs and SoCs:
The three DSP block modes available are as follows:
A single DSP block in the floating-point mode provides an IEEE 754 single-precision floating-point multiplier and an IEEE 754 single-precision adder, delivering the highest floating-point performance on any FPGA in the market. These floating-point operators allow floating-point designs to be similar to traditional fixed-point designs, providing the benefits of floating-point at no additional cost for FPGA designers. Also, designers are able to remain in floating point, eliminating months of converting algorithms to fixed point and verifying the accuracy.
The floating-point mode offers:
- An IEEE 754 single-precision multiplier and IEEE 754 single-precision adder in each DSP block
- Support for floating-point operations, such as: AxB, A+C, A-C, AxB+C, AxB-C, Acc=AxB+Acc
- Vector operations to support convolution, dot products, and other linear algebra functions
- Complex multiplication using fast Fourier transform (FFT)
In addition to floating-point capabilities, the new variable prevision block includes:
- Internal pipeline registers for faster fMAX and lower power consumption
- 108 inputs, 74 outputs
- 18x19 multiply mode, allowing the pre-adder to use two 18 bit inputs
- Optional second accumulator (feedback register) for complex serial filtering
- Dual 18x19 independent multipliers
- Built-in 18 bit or 28 bit coefficient register banks, available with or without the pre-adder function
All DSP block modes feature a 64 bit accumulator and each variable-precision DSP block comes with a 64 bit cascade bus. The cascade bus allows the implementation of even higher precision signal processing through cascading multiple blocks using a dedicated bus.
The variable-precision DSP architecture maintains backward compatibility. It can efficiently support existing 18 bit DSP applications, such as high-definition video processing, digital up- or down- conversion and multirate filtering.
A complete suite of tools to accelerate designer’s productivity include model-based, C-based, and HDL/IP-based design entry
- DSP Builder for Intel® FPGAs (Simulink-based)
- Intel FPGA SDK for OpenCL™ (C-based)
- Quartus® Prime (HDL/IP-based)
Need even more floating-point performance? Arria® 10 designs offer a seamless design and device migration path to Stratix 10 devices offering up to 10 TFLOPS of performance. For more information, contact your local sales representative.
- Arria 10 FPGAs
- Arria 10 SoCs
- Arria 10 Family Overview Table
- The Industry's First Floating-Point FPGA (PDF)
- Model-based approach for floating-point designs with DSP Builder for Intel FPGAs
- Webcast: Accelerating Design Development Time with Hard Floating-Point DSP Blocks in FPGAs
- Technical White Paper: Understanding Peak Floating-Point Performance Claims