The architectural innovation in the implementation of IEEE 754 single-precision hardened floating-point DSP (digital signal processing) blocks in Arria® 10 FPGAs and SoCs enable processing rates up to 1.5 TFLOPs (Tera Floating-point Operations Per Second) and power efficiency up to 40 GFLOPs/Watt.
With the three modes available for Arria® 10 DSP blocks: standard-precision fixed-point, high-precision fixed point and single-precision floating-point, designers can implement a variety of algorithms that require fixed point all the way to double-precision IEEE 754 compliant floating-point operations. Hardened floating-point processing offers designers the ability to implement algorithms in floating point with the similar performance and power efficiency as fixed point. This can be achieved without any power, area, or density compromises and with no loss of fixed-point features or functionality.
Arria 10 FPGAs and SoCs are a compelling solution for industrial, wireless systems, compute intensive applications such as high performance computing, machine learning, high-precision radars and data center acceleration applications.
Learn more about the floating-point processing capabilities for Arria 10 FPGAs and SoCs: