On the system side interface, a Stratix® IV FPGA is capable of providing a 100G chip-to-chip interface through the Interlaken protocol via 20 lanes running at 6.375 Gbps. The solution shown in Figure 1 provides a dedicated 100G datapath from the line side to the system side. The flexibility of deploying an FPGA allows you to leverage your own proprietary bus interfaces on the system side. You can bridge between your proprietary interfaces to industry-standard Interlaken interfaces. The Interlaken solution is provided by Sarance, and is compliant with the Interlaken Alliance specification standards.
The solution shown in Figure 1 leverages the current ecosystem and third-party multi-lane distribution (MLD)multiplexed PHYs to provide an industry-standard 100G platform on a 40-nm technology node. Altera is committed to providing the optimal solution for implementing 100G on networking platforms.
The solution shown in Figure 2 leverages the transceiver technology leadership to operate at 10.3125 Gbps and eliminates the need for an external 10G PHY device capable of providing MLD features. This solution proves a true single FPGA 100G solution, where the 100G CFP optical module can directly interface with the Altera® Stratix IV GT FPGA.
The current industry trend is to use Ethernet over WDM for packet transport and IP/MPLS/Ethernet for data transport. Altera’s 40-nm Stratix IV FPGAs are well positioned to meet the performance and system bandwidth requirements for 100G Ethernet and transport system designs. Stratix IV GT FPGAs provide the highest density with integrated 11.3-Gbps transceivers which are essential for 100 GbE/Fibre Channel/RPR MAC functions into a single device, as well as handle key functions like forward error correction (FEC), mapping, and framing of optical transport network (OTN) packets. The OTU-4 standards for 100 GbE use enhanced FEC, which must be designed with specific algorithms to ensure that you can use the optical bandwidth to its fullest extent. Due to its superior fabric performance, Stratix IV FPGAs can handle the enhanced FEC functions as well, making them an ideal platform for OTN systems designed for algorithm implementation and testing. Table 1 shows the supported Stratix IV GX transceiver protocols for OTN applications.
Table 1. Stratix IV GX Transceiver Protocols for OTN Applications
100G OTN Designs with Stratix IV GT FPGAs
Recent standards activities are aligning around OTN-4 for 100G optical transport. These applications demand a combination of high-speed 10G transceivers to support the necessary throughput requirements, as well as core performance and logic density to handle the complex processing needed for managing 100G data traffic. Stratix IV GT devices, with integrated 11.3-Gbps transceivers, enable direct connection to a 10G optical interface on the client side, as well as a direct connection to 100G CFP or QSFP modules on the network side. This is a key benefit because it eliminates the use of external PHY devices and simplifies overall system complexity. In addition, the devices support bonded interfaces such as MLD and SFI-S for chip-to-module and chip-to-chip connections. Equipment manufacturers can develop early versions of OTN-4 muxponders, transponders, and regenerators as the standards within the International Telecommunication Union (ITU) and Optical Internetworking Forum (OIF) evolve. Table 2 shows supported Stratix IV GT transceiver protocols for OTN applications.
Table 2. Stratix IV GT Transceiver Protocols for OTN Applications
|Protocol||Data Rate (Gbps per Lane)|
|100G IEEE 802.3ba||10.3125|
|10G IEEE 802.3ae||10.3125|
|40G IEEE 802.3ba||10.3125|
|OTN-2||9.9 to 11.3|
|OTN-3||9.9 to 11.3|
|OTN-4||9.9 to 11.3|
|OTN-4 MLD||9.9 to 11.3|
|SFI-S (includes SFI-5.2)||9.9 to 11.3|
|SONET/SDH OC192/STM-64||9.9 to 11.3|