Stratix III—The World's Fastest 65-nm FPGAs

Altera's Stratix® III devices are the world's lowest power high-performance 65–nm FPGAs. Recent benchmarks on a wide variety of real customer applications show significant performance advantage increases over results originally published in Q4 of 2006.

The improvements are due to new performance optimization techniques in Quartus® II software and updated timing models that reflect the faster Stratix III silicon correlation results.

The new benchmarks show that Stratix III FPGAs are:

Meet Your High-Performance Requirements Using Slower Speed Grades

Figure 1 and Table 1 show how you can actually meet your design's high-performance requirements using slower speed grades of Stratix III FPGAs.

Figure 1. Performance Comparison by Speed Grade

Figure 1. Performance Comparison by Speed Grade

Table 1. Performance Comparison by Speed Grade

Stratix III FPGA
Speed Grade
Nearest Competing FPGA
Speed Grade
Stratix III Performance Advantage
FastNone Available25% faster than nearest competitor's fast-speed grade
MediumNone Available10% faster than nearest competitor's fast-speed grade
SlowFastParity
0.9 Volt, Lowest PowerSlowParity

Stratix III FPGA Performance Advantage Increases with Design Size

Figure 2 shows a plot of the fMAX ratio between Stratix III and Virtex-5 FPGAs on the y-axis and the design size on the x-axis. Each data point represents a real customer design. The results show:

  • The fMAX ratio increases with design size because of a performance degradation in Virtex-5 FPGAs
  • Stratix III FPGA performance advantage over Virtex-5 quickly increases from 25% to 50% as the design size increases
Figure 2. Altera's Performance Advantage Increases with Design Size

Table 2. Altera's Performance Advantage Increases with Design Size

Design Size (Logic Elements) All Circuits 50K - 75K 75K - 125K > 125K
Stratix III Advantage+25%+39%+55%N/A (1)

Note:

  1. Too many large designs failed to compile on the competitor's software to have a statistically valid sample.

Stratix III Performance Not Compromised with Utilization

Figure 3 compares the performance of a parameterized customer design in Stratix III and Virtex-5 FPGAs. The size of this design was increased by varying a parameter. Each data point in Figure 3 shows a different parameterization of the design, resulting in a different logic utilization shown on the x-axis. The achieved performance (fMAX) is on the y-axis. The results for the same design show:

  • Stratix III FPGAs have no performance degradation as the FPGA fills up
  • ISE Foundation software is unable to fit designs larger than 65% of the device
  • A 45 percent performance degradation is seen in Virtex-5 FPGAs when the device is half full
Figure 3. No Performance Degradation in Stratix III FPGAs

Additionally, the high-speed core of Stratix III FPGAs is also supported by fully optimized on-chip memory and I/O interfaces. Tables 3 and 4 show comparisons of 65-nm FPGA on-chip memory and I/O interface speeds.

Table 3. Stratix III FPGA Performance

Feature Stratix III
(65 nm)
Virtex-5
(65 nm)
Maximum Internal Clock Speed600 MHz550 MHz
On-Chip RAM600 MHz550 MHz
Digital Signal Processing (DSP) Block550 MHz550 MHz

Table 4. Stratix III I/O Performance

Interface Stratix III
(65 nm)
Virtex-5
(65 nm)
DDR2400 MHz333 MHz
DDR3533 MHzNo DIMM Support
QDR II350 MHz300 MHz
QDR II+350 MHzNot Supported
RLDRAM II400 MHz300 MHz
LVDS1.60 Gbps1.25 Gbps

Benchmarking Methodology

All benchmarking data on this page is based on comparing an Altera® FPGA to the equivalent, nearest competing FPGA, and using the latest available version of software at the time of analysis.

Altera has a third-party, industry-expert-endorsed performance benchmarking methodology, which is used to compare FPGA performance between families from a single FPGA vendor and with those of competitive solutions. This ensures a consistent benchmarking environment when testing Altera FPGAs and when comparing them to competitor FPGAs.