Table 1: I/O Standards Supported by Stratix Series FPGA Families
For more details, see:
- I/O Interfaces section of the Stratix IV (PDF) Handbook
- I/O Interfaces section of the Stratix III (PDF) Handbook
- I/O Standards section of the Stratix II (PDF) and Stratix II GX (PDF) Handbook
- I/O Standards section of the Stratix (PDF) and Stratix GX (PDF) Handbook
Stratix series FPGA I/O pins have the system-level performance and flexibility required to communicate with a multitude of devices. Intellectual property (IP) cores, and software tools such as Timing Analyzer, simultaneous switching noise (SSN) estimator, and pin planner all aid in ease of use and rapid integration.
Stratix series FPGA I/Os support high-performance, DC-coupled LVDS transmit and receive channels. In some families, each high-speed, side I/O LVDS pair has a hard dynamic phase alignment (DPA) block to eliminate clock-to-channel and channel-to-channel skew. Stratix series FPGA high-speed LVDS I/O pins support interface standards such as SPI-4.2, SFI-4, SGMII, Utopia IV, 10 GbE XSBI, the RapidIO® standard, and SerialLite.
Single-Ended I/O Support
The Stratix series FPGA single-ended I/O feature supports:
- Programmable slew rate and drive strength
- Dynamic trace compensation (variable delay chains for board trace mismatch compensation on both input and output signals)
- Serial, parallel, and dynamic on-chip termination (OCT)
For more information about OCT see Termination Solutions in Stratix Series FPGAs.
High-Speed External Memory Interfaces
Stratix series FPGA I/O pins support existing and emerging external memory standards such as DDR, DDR2, DDR3, QDRII, QDRII+ and RLDRAMII at frequencies up to 400 MHz (see External Memory Interface Resources for Stratix Series FPGAs). A self-calibrating datapath takes advantage of the new I/O structure, dynamically adjusting itself to always provide the highest reliable frequency of operation across process, voltage, and temperature.
The Stratix series FPGA external memory interfaces feature supports:
- SDR and half data rate (HDR–half the frequency and twice the data width of SDR) input and output options
- HDR block with alignment and synchronization
- De-skew, read/write leveling and clock-domain crossing functionality
See the Stratix Series External Memory page for details of supported memories and data-rates.
Stratix Series FPGA I/O banks delivers signal integrity, low SSN, and superior eye quality through many chip-level and package-level enhancements. For more details see the Signal Integrity Technology Center web pages.
- I/O Interfaces section of the Stratix IV Handbook (PDF)
- I/O Interfaces section of the Stratix III Handbook (PDF)
- I/O Standards section of the Stratix II Handbook (PDF)
- I/O Standards section of the Stratix II GX Handbook (PDF)
- I/O Standards section of the Stratix Handbook (PDF)
- I/O Standards section of the Stratix GX Handbook (PDF)
- External Memory Interfaces in Stratix Series Devices