Fractional phase-locked loops (fPLLs) offer all the features available in previous-generation Altera® PLLs. You can find fPLLs in Altera's 28-nm devices, including Stratix® V, Arria® V, and Cyclone® V FPGAs. New capabilities are shown in Table 1.
Precision Fractional Frequency Synthesis
A major innovation in our 28-nm devices is the integration of fPLLs into the device architecture. All general-purpose PLLs are implemented as fPLLs, capable of advanced fractional frequency synthesis, as well as standard M/N multiplication. Depending on device density, up to 32 fPLLs are available for general-purpose use. Figure 1 provides a block diagram of the fPLL.
To implement a fPLL, the delta-sigma modulator is turned on. This allows the feedback M divider to take on fractional values, which allows precision frequency synthesis. When used as a standard M/N PLL, both M and N values are integers and the delta-sigma modulator is disabled.
Optical transport network (OTN) multiplexing transponder (muxponder) applications generally require expensive VCXOs that synthesize the various client frequencies from information embedded in the aggregate data stream. The fPLLs are designed to replace these VCXOs, resulting in a cost-effective, highly integrated solution. As shown in Figure 2, the client frequency information in the aggregate data stream is used to control the delta-sigma modulators in the fPLLs, allowing for precise synthesis of the required client line rate frequencies.
Systems that include serial communication protocols require precision reference clock sources at both ends of the serial link. Typically, these reference clocks are generated using multiple crystal oscillators on the circuit board. In our 28-nm FPGAs, the precision frequency synthesis capability of the fPLLs can be used to replace these reference clock oscillators. Figure 3 shows an application using a Stratix V FPGA, where several board-level frequency references (OSC_1 thru OSC_n) can be replaced by a single frequency reference (OSC) and multiple on-chip fPLLs that synthesize the required reference clock frequencies.
At data rates up to 3.75 Gbps, the fPLLs can be used directly as transceiver transmit PLLs. This increases the total number of transmit PLLs available in each device. At data rates above 3.75 Gbps, the fPLLs can be used to synthesize the reference clocks which are then applied, via PLL cascading, to the high-speed transmit PLLs.