Because Stratix® V FPGAs enable the highest system integration, you get increased functionality in a smaller FPGA, lowering power and cost. Here, we'll discuss a number of Stratix V innovations that make this level of integration possible.
Embedded HardCopy Blocks
Embedded HardCopy® Blocks are customizable hard intellectual property (IP) blocks that utilize Altera’s unique HardCopy ASIC capabilities. This innovation substantially increases FPGA capabilities by:
- Dramatically increasing density per area
- Offering up to 14.3M gates, or up to 1.19M logic elements (LEs)
- Increasing performance and lowering power
Embedded HardCopy Blocks are used to harden standard or logic-intensive functions such as interface protocols, application-specific functions, and proprietary custom IP functions. See Figure 1 for a diagram of Embedded HardCopy Blocks.
Figure 1. Customizable Embedded HardCopy Block
Altera has used Embedded HardCopy Blocks to create a new class of application-targeted Stratix V variants optimized for:
- Bandwidth-centric applications and protocols, including PCI Express® (PCIe®) Gen3, Gen2, and Gen1
- Data-intensive applications for 40G/100G and beyond.
The hardened blocks for these applications and protocols are shown in Table 1.
Table 1. Hard IP Functions Built with the Embedded HardCopy Block
|PCIe Gen3, Gen2, Gen1||PHY/MAC, data link, transaction layers|
|40G/100G||MLD/PCS – gearbox, block sync,
alignment marker, reorder virtual channel,
async buffer/deskew, block striper/destriper,
Integrated Hard IP Blocks in Transceivers and Core
Stratix V FPGAs harden specific digital functionality in the physical coding sublayer (PCS) per transceiver channel for a number of key protocols used in backplane, line card, and chip-to-chip applications. Additionally, the FPGA core also includes hard IP blocks like the new variable-precision digital signal processing (DSP) and memory blocks for high-performance applications. See Table 2.
Table 2. Integrated Hard IP Blocks in Transceivers and Core
|Hard IP Per Transceiver Channel (PCS)|
|Interlaken||Gearbox, block sync, 64B/67B, frame sync,
|10 Gigabit Ethernet (GbE) (10GBASE-R)||Gearbox, block sync, scrambler/descrambler,
64B/66B, rate matcher
|PCIe Gen3, Gen2, Gen1||Word aligner, lane sync state machine, deskew,
rate matcher, 8B/10B, gearbox, 128B/130B, PIPE-8/16/32
|Serial RapidIO® 2.0||Word aligner, lane sync state machine, deskew, rate matcher, 8B/10B|
|CPRI/OBSAI||Word aligner, bit slip (determinist latency), 8B/10B|
|Core Hard IP|
|DSP||Up to 3,510 new high-performance, variable-precision DSP blocks in the core|
|Embedded Memory||Up to 2,560 M20K embedded memory blocks|
In an analysis of an actual customer application, we've found that by implementing 24 channels of Interlaken and 2 PCIe Gen3 x8 cores, a Stratix V FPGA with 240K LEs is equivalent to a traditional FPGA with 610K LEs. See Figure 2.
Figure 2. LE Savings with Interlaken Implementation
Implementing 24 channels of Interlaken saves about 120K LEs in the PCS. Implementing two PCIe Gen3 x8 hard IP functions saves about 250K LEs and associated memories. Together, this is a total savings of 370K LEs. Given this, you can use a smaller FPGA for your application, reducing cost and power consumption, or integrate more functionality on a single chip. See Table 3.
Table 3. Interlaken Savings Implementation
|Hardened IP for Protocol||Logic Element Savings|
|24 Channels of Interlaken||120K|
|2 PCIe Gen3 x8 Cores||250K|
|Total LE Savings||370K|