Ultimate Flexibility Through Partial & Dynamic Reconfiguration

With Stratix® V FPGAs, you can easily change the core and transceiver functionality on the fly while other portions of your design are still running. This flexibility is enabled by:

  • User-friendly fine-grain partial reconfiguration, which requires less development time and effort than competing solutions.
  • Dynamically reconfigurable transceivers, which let you easily support multiple protocols, data rates, and physical medium attachment (PMA) settings.

Figure 1: Partial and Dynamic Reconfiguration in Stratix V FPGAs

Having this level of flexibility is imperative for high-bandwidth applications like 100G OTU-4 multiplexing transponders (muxponders) that support multi-standard client interfaces from 150 Mbps to 28 Gbps. By designing such applications with Stratix V FPGAs, you can update or adjust the functionality of the FPGA on the fly, without disrupting services to all of your clients.

Additionally, to increase your competitive edge, you need to be able to constantly incorporate more functionality and system performance in your FPGA-based designs. Often, this requires a large FPGA that not only increases costs but also power. Partial reconfiguration improves effective logic density by removing the need to place in the FPGA functions that do not operate simultaneously. Instead, you can store these functions in external memory and load them as needed. This reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and cost, and reducing power consumption.

Partial Reconfiguration Implementation

To date, competitive implementations of partial reconfiguration capabilities have required much longer engineering cycles and far more design flow complexity, including a need to know all the intricate FPGA architecture details. Altera has simplified the partial reconfiguration process with:

  • A state-of-the-art new reconfigurable fabric in the Stratix V FPGA
  • A design built on top of the proven incremental compile design and Logic Lock Region flows in Quartus® Prime design software

With our implementation of partial reconfiguration, you don't need to have intricate knowledge of the FPGA. There is no limit to the number of regions (partitions) and programming files and no restrictions to the order of loading the partitioned region in the FPGA. Additionally, for minimal design changes, you can use partial reconfiguration without the need to partition your entire design.

Partial reconfiguration is supported through any of the following configuration schemes:

  • Flash Parallel X16 interface
  • Internal processor such as the Nios® II embedded processor
  • Configuration through any external interface (including PCI Express® (PCIe®) and Gigabit Ethernet)
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Introduction to Partial Reconfiguration

  • Learn about the partial reconfiguration design flow
  • Understand the sequence of operations and software features of partial reconfiguration
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View Video

Stratix V FPGA Partial Reconfiguration and Transceiver Reconfiguration Design Demo

  • Learn how 28 nm Stratix V FPGAs provide the capability to reconfigure a user-specified portion of the core using partial reconfiguration
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