Arria II FPGA Transceiver Overview

Arria® II FPGAs with embedded transceivers deliver excellent system bandwidth and power efficiency for cost- and power-sensitive transceiver-based applications. The transceivers are based on 40-nm technology and include a number of features that ensure excellent jitter performance combined with superior signal integrity for both backplane and chip-to-chip applications. Arria II transceivers are optimized for cost and power, and support standard, emerging, and proprietary serial protocols up to 6.375 Gbps. The transceivers include several digital blocks that you can configure to simplify the implementation of these protocols.

Key Transceiver Features

  • Arria II GX FPGA: Up to 16 transceivers with clock data recovery (CDR), supporting data rates from 600 Mbps to 6.375 Gbps
  • Arria II GZ FPGA: Up to 24 transceivers with CDR, supporting data rates from 600 Mbps to 6.375 Gbps
  • Flexible and easy to configure transceiver datapath to implement industry standard and proprietary protocols
  • Programmable pre-emphasis settings and adjustable differential output voltage (VOD) for improved signal integrity
  • Five stages of user-controlled receiver equalization with up to 7 dB of gain to compensate for frequency-dependent losses in the physical medium
  • Dynamic reconfiguration of the transceiver to support multiple protocols and data rates on the same channel without reprogramming the FPGA
  • Support for protocol features such as MSB to LSB transmission in SONET/SDH configuration and spread-spectrum clocking in PCI Express (PIPE) configuration
  • Dedicated circuitry compliant with the physical interface for PCI Express (PIPE), XAUI, and gigabit Ethernet
  • Arria II GX FPGA: PIPE interface connects directly to embedded PCI Express Gen1 (2.5 Gbps) hard intellectual property (IP) or to soft IP
  • Arria II GZ FPGA: PIPE interface connects directly to embedded PCI Express Gen1 and Gen2 (5.0 Gbps) hard intellectual property (IP) or to soft IP
  • Each transmitter has two phase-locked loop (PLL) inputs and independent clock dividers to allow different clock rates for each channel
  • Built-in byte ordering so that a frame or packet always starts in a known byte lane
  • 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
  • On-die power supply regulators for transmitter and receiver PLL charge pump and voltage controlled oscillator (VCO) for superior noise immunity
  • On-chip power supply decoupling to satisfy transient current requirements at higher frequencies, which reduces the need for on-board decoupling capacitors
  • Diagnostic features such as serial loopback, parallel loopback, reverse serial loopback, and loopback master and slave capability in PCI Express hard IP blocks

Block Diagram

Figure 1 shows the block diagram of the Arria II transceivers, both physical medium attachment (PMA) and physical coding sublayer (PCS). The blocks within the PCS can be bypassed, depending on your requirements.

Figure 1. Arria II Transceivers, PMA, and PCS Block Diagram

Arria II transceivers include dedicated circuitry to implement standard and proprietary protocols operating between 600 Mbps and 6.375 Gbps. The transceivers are also capable of supporting data rates as low as 270 Mbps using oversampling, which is important when supporting legacy protocols and protocols with multiple data rates. When augmented with Altera® IP, Arria II transceivers provide a complete, low-risk solution for serial protocol implementation.

Arria II Signal Integrity

Arria II transceivers are architected to deliver excellent signal integrity characteristics, at low cost and power. Figure 2 shows the signal integrity of Arria II transceivers at 6.375 Gbps.

Figure 2. Arria II GX Eye Diagram at 3.75 Gbps

Arria II Supported Protocols

Table 1 provides information about the protocols supported by Arria II FPGAs.

Table 1. Supported Protocols

Standards Arria II GX Arria II GZ
PCI Express Gen12.52.5
PCI Express Gen2-5.0
PCI Express Cable2.52.5
SDI SD/HD0.27, 1.4880.27, 1.488
Serial RapidIO1.25, 2.5, 3.1251.25, 2.5, 3.125
Gigabit Ethernet1.251.25
10G Ethernet (XAUI)3.1253.125
Fibre ChannelUp to 2.25Up to 4.25
GPON1.244 uplink, 2.488 downlink1.244 uplink, 2.488 downlink
Interlaken-Up to 6.375
SONET OC-3 / OC-12 / OC-480.155, 0.622, 2.4880.155, 0.622, 2.488
CPRI0.6144, 1.2288, 2.45, 3.072, 6.1440.6144, 1.2288, 2.45, 3.072, 6.144
OBSAI0.75, 1.536, 3.072, 6.1440.75, 1.536, 3.072, 6.144
Serial ATA (SATA) Gen1, Gen2, and Gen31.5, 3.0, 6.01.5, 3.0, 6.0
Serial Attached SCSI (SAS) Gen1 and Gen23.0, 6.03.0, 6.0
Basic ModeUp to 6.375Up to 6.375
SerialLite IIUp to 6.375Up to 6.375