Cyclone IV GX FPGAs: Transceiver Overview

Altera’s Cyclone® IV FPGA family extends the Cyclone FPGA series leadership in providing the market’s lowest cost, lowest power FPGAs, now with transceivers.

Not all low-cost transceivers are created equally. The Cyclone IV GX FPGA was specifically designed to allow the implementation of multiple protocols in a single quad and to allow independent receive and transmit frequencies. This flexibility helps you fully utilize all available transceiver resources and keep designs in a smaller and lower cost device.

Key Transceiver Features

  • Up to eight transceivers with clock data recovery (CDR), supporting data rates from 600 Mbps to 3.125 Gbps
  • Flexible and easy-to-configure transceiver datapath to implement industry-standard and proprietary protocols
  • Programmable pre-emphasis settings and adjustable differential output voltage (VOD) for improved signal integrity
  • User-controlled receiver equalization to compensate for frequency-dependent losses in the physical medium
  • Dynamic reconfiguration of the transceiver to support multiple protocols and data rates on the same channel without reprogramming the FPGA
  • Support for protocol features such as spread-spectrum clocking in PCI Express®, DisplayPort, V-by-One, and SATA configurations
  • Dedicated circuitry compliant with the physical interface for PCI Express, XAUI, and Gbps Ethernet
  • PIPE interface that connects directly to embedded PCI Express Gen1 (2.5 Gbps) hard intellectual property (IP) to support PCI-SIG® compliant x1, x2, or x4 endpoint or rootport applications
  • Two phase-locked loop (PLL) inputs on each transmitter; the EP4CGX50 device and larger devices also have independent clock dividers to allow different clock rates for each channel
  • Built-in byte ordering so that a frame or packet always starts in a known byte lane
  • 8B/10B encoder and decoder that performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
  • On-die power supply regulators for transmitter and receiver PLL charge pump and voltage controlled oscillator (VCO) for superior noise immunity
  • On-chip power supply decoupling to satisfy transient current requirements at higher frequencies, which reduces the need for on-board decoupling capacitors
  • Diagnostic features such as serial loopback, parallel loopback, reverse serial loopback, and loopback master and slave capability in the PCI-SIG compliant PCI Express hard IP block

The following figure shows the block diagram of the Cyclone IV GX transceivers, both physical medium attachment (PMA) and physical coding sublayer (PCS). The blocks within the PCS can be bypassed, depending on your requirements.

Cyclone IV GX Transceivers, PMA & PCS Block Diagram

Cyclone IV GX Supported Protocols


148-pin QFN, 169-pin FBGA, and 324-pin FBGA Packages
(Data Rate in Gbps)

484-pin FBGA, 672-pin FBGA, and 896-pin FBGA Packages
(Data Rate in Gbps)


Up to 2.5 Up to 3.125
PCI Express Gen1 2.5 2.5


1.25 1.25
SDI SD/HD - 0.27, 1.488
3G-SDI - 2.97
Serial RapidIO® - 1.25, 2.5, 3.125
10GbE (XAUI) - 3.125
CPRI - 0.6144, 1.2288, 2.45, 3.072


- 0.75, 1.536, 3.072

Serial ATA (SATA) Gen1, Gen2

- 1.5, 3.0

3G Basic

- Up to 3.125


1.62 2.7


- 3.0