Stratix V GX/GS FPGAs are designed for backplane applications. Altera’s Stratix V GX/GS transceivers offer a number of programmable and adaptive equalization features designed to handle the challenges of backplane links including:
- 4-tap transmit pre-emphasis
- Continuous time-linear equalizers (CTLE)
- Adaptive decision feedback equalizers (DFE)
These solutions are designed to provide the most amount of flexibility and performance at the lowest power in an FPGA transceiver to address the range of problems that are encountered in backplane applications, including 10GBASE-KR backplanes. For more information, please read our whitepaper on Backplane Applications with 28 nm FPGAs (PDF) as well as our application notes on designing high-speed PCBs for backplane applications.
Stratix V FPGAs feature up to 66 full-duplex transceiver channels, with transceivers at data rates from 14.1 Gbps to 28.05 Gbps. Providing up to over 930 Gbps of transceiver bandwidth, Stratix V FPGAs deliver the highest system bandwidth at the lowest power consumption for a wide range of applications and protocols. In addition, the transceivers are compliant with a range of protocols and are equipped with a variety of signal conditioning features to support backplane, optical module, and chip-to-chip applications. See our best-in-class transceiver eye diagrams at 14.1 Gbps and 28 Gbps shown in Figure 1 and Figure 2.
Figure 1. Stratix V GS/GX 14.1 Gbps Eye Diagram
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Figure 2. Stratix V GT 28 Gbps Eye Diagram
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Stratix V transceivers also include full-featured embedded physical coding sublayer (PCS) hard intellectual property (IP) to simplify design, lower power, and save valuable core resources. The Stratix V FPGA transceiver channel consists of the physical media attachment (PMA), PCS, and hardened IP blocks with added clocking flexibility and more independent channels. Each channel has a full PMA and PCS along with a dedicated, independent receive analog PLL CDR. You'll have access to an abundant number of transmit clocking sources, including the wide data range support of the clock multiplication unit (CMU) as well as the low-jitter LC transmit PLLs. Plus, you can minimize the number of off-chip crystal oscillators by utilizing the new fractional PLLs (fPLLs) with precise frequency synthesis. Not only can the fPLLs generate fractional multiples of a reference clock, they can also be used to drive the transceiver reference clock. Figure 3 shows some of the key architectural features for Stratix V FPGA transceivers.