Intel® MAX® 10 FPGAs offer system-level cost savings through increased integration of external system component functions. Unlike CPLDs, 55 nm MAX 10 FPGAs include full-featured FPGA capabilities, such as digital signal processing (DSP), analog blocks with analog-to-digital converters (ADCs) and a temperature sensor, embedded soft processor support, memory controllers, and dual configuration flash.
View the MAX 10 FPGA Product Table.
- Up to 50,000 logic elements (LEs)
- Up to 500 user I/O pins
- Non-volatile instant-on architecture
- Single chip
- Packages as small as 3x3 mm2
- Embedded SRAM
- DSP blocks
- High-performance phase-locked loops (PLLs) and low-skew global clocks
- External memory interface (DDR3 SDRAM/DDR3L SDRAM/DDR2 SDRAM/LPDDR2)
- Nios® II soft core embedded processor support
- 3.3 V, LVDS, PCI*, and 30+ other I/O standards supported
- Embedded SAR ADCs – 12 bit, 1 Msps
- Up to 18 analog input channels
- Temperature sensor
- Single or dual-core voltage supply offering
- Embedded flash
- Dual configuration flash
- User flash memory
- Internal oscillator
- Power-saving features
- Sleep mode to reduce dynamic power by up to 95%
- Input buffer power-down
- 128 bit Advanced Encryption Standard (AES) and other design security features
- RoHS6 packaging
1. Additional user flash may be available, depending on configuration options.
2. The number of PLLs available is dependent on the package option.
3. Availability of the ADC or TSD varies by package type. Smaller pin-count packages do not have access to the ADC hard IP.
4. SRAM only.
5. SRAM, DDR3 SDRAM, DDR2 SDRAM, or LPDDR2.
6. “D” = Dual power supply (1.2 V/2.5 V), “S” = Single power supply (3.3 V or 3.0 V).
7. V81 package does not support analog feature set. 10M08 V81 F devices support dual image with RSU.
8. “Easy PCB” utilizes 0.8 mm PCB design rules.
9. All data is correct at the time of printing, and may be subject to change without prior notice.
MAX 10 FPGAs are available in commercial, industrial, and automotive (AEC-Q100) temperature grades.
In addition, they will be supported in a future release of the functional safety pack, TUV Certified to IEC 61508 and ISO 26262, reducing development time and time to market.
- MAX 10 FPGAs - Revolutionizing Non-Volatile Integration (PDF)
- Advanced System Management with Analog Non-Volatile FPGAs (PDF)
- Five Ways to Build Flexibility into Industrial Applications with FPGAs (PDF)
- Lowering the Total Cost of Ownership in Industrial Applications (PDF)
- How to Design for Increasing Power Constraints (PDF)
- Nios® II Processor Documentation