The Intel® Quartus® Prime design software delivers the highest performance, highest logic utilization, and fastest compile times for high-end FPGA designs. The Quartus Prime software is equipped with new algorithms and technologies to scale the range of densities and features offered by next-generation FPGAs.

The Intel FPGA SDK for OpenCL™ combines Open Computing Language (OpenCL), an open standard parallel programming language, with the parallel performance capabilities of an FPGA to provide a powerful solution for system acceleration.

 

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. 

Quartus Prime Design Software

FPGA design software for the next generation of FPGAs such as Intel Stratix® 10 FPGAs and SoCs requires a new approach. Tighter timelines are driving the need for faster compile times, reduced design iterations, and faster design entry for both hardware and software designers. Stringent design requirements are driving the need for more sophisticated tools for design planning and timing closure. The Quartus Prime software boosts designer productivity and accelerates time to market for Stratix 10 devices.

Stratix 10 FPGAs and SoCs feature new hardware innovations specifically architected with the flexibility and modularity needed for true hierarchical design. Key features of the Quartus Prime software designed for significantly higher productivity are:

  • The new Intel HyperFlex™ FPGA Architecture, with registers everywhere throughout the interconnect to achieve 2X the performance of previous generation FPGAs
  • Programmable clock tree synthesis
  • A sector-based approach to device configuration

The Quartus Prime software takes advantage of this flexibility and modularity to dramatically reduce the number of design iterations, enable extensive design reuse and facilitate architectural exploration and planning.

 Key features include:

  • Faster time to market with up to 10X reduction in design iterations
  • Instant, legal serial I/O and memory interface placement with BluePrint Platform Designer
  • Productivity increased with 8X faster compile times
  • Versatile design entry for both hardware and software design entry methods
  • HyperFlex FPGA Architecture Optimized tools - Hyper-Aware design flow including post Place and Route Hyper-Retiming and Fast Forward Compile 
     

Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.

Fast Forward Compile

Achieve 2X Peformance Breakthroughs

Intel® Stratix® 10 FPGAs deliver a breakthrough leap in core performance. Users can now unlock design performance by taking advantage of the innovative capabilities of the HyperFlex™ FPGA Architecture, reaching breakthrough levels of performance not possible in previous-generation FPGA architectures. Developed to enable 2X performance in customer designs†, the Fast Forward Compile feature pinpoints performance bottlenecks and provides detailed, step-by-step performance improvement recommendations that a user can implement rapidly. Users also receive fMAX (maximum operating frequency) estimates of their design that can be achieved by applying the recommendations Fast Forward Compile provides. With this innovative design flow, Fast Forward Compilation gives customers an opportunity to maximize the overall design performance made possible by Stratix 10 FPGAs and achieve rapid timing closure.

Productivity Advantages with Fast Forward Compile

Previously, to achieve high-performance targets users often needed to undergo multiple, time-consuming design iterations, including trying various design optimizations and re-running a full FPGA compile to determine the effectiveness of design changes. With Fast Forward Compile, users receive detailed guidance for design optimization and an estimated design fMAX to leverage the HyperFlex FPGA Architecture. With these insights, customers are able to make better decisions about where to invest development time most effectively to increase design performance and throughput, taking the guesswork out of performance exploration. As a result, Stratix 10 customers perform fewer design iteration cycles to achieve their performance targets and simplify the path to achieving 2X core performance gains.

Contact your local sales representative about evaluating Fast Forward Compile >>

Register Now!

Register for Training on the HyperFlex FPGA Architecture

Intel offers insructor-led training and online training courses covering design optimization techniques to extract the maximum performance from your design using the HyperFlex FPGA Architecture.

Register now to schedule instructor-led training or to view free online training now.

 

 

Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.