Stratix® 10 FPGAs and SoCs deliver the highest performance along with the highest levels of sytem integration. Learn more about the unique capabilities and breakthrough advantages that Stratix 10 devices deliver to enable next-generation, high-performance systems in a wide-range of applications  below.

HyperFlex Architecture Overview

To address the challenges presented by next-generation systems, Stratix 10 FPGAs and SoCs feature the new HyperFlex™ core architecture, which delivers 2X the clock frequency performance and up to 70% lower power compared to previous-generation, high-end FPGAs.

HyperFlex Architecture Benefits

Higher Throughput Greater Design Functionality
  • Leverage 2X core clock frequency performance to obtain throughput breakthroughs
  • Use faster clock frequencies to reduce bus widths and reduce intellectual property (IP) size, freeing up additional FPGA resources to add greater functionality
Improved Power Efficiency Increased Designer Productivity
  • Use reduced IP size—enabled by the  HyperFlex architecture—to consolidate designs spanning multiple devices into a single device, thereby reducing power by up to 70% versus previous-generation devices
  • Boost performance with less routing congestion and fewer design iterations using Hyper-Aware design tools
  • Obtain greater timing margin for more rapid timing closure

The HyperFlex architecture introduces additional bypassable registers everywhere throughout the FPGA fabric. These additional registers, called Hyper-Registers, are available on every interconnect routing segment and at the inputs of all functional blocks.  Hyper-Registers enable three key design techniques to achieve the 2X core performance increase:

  • Fine grained Hyper-Retiming to eliminate critical paths
  • Zero latency Hyper-Pipelining to eliminate routing delays
  • Flexible Hyper-Optimization to achieve best-in-class performance

When you use these techniques in your design, the Hyper-Aware design tools automatically use the Hyper-Registers to achieve maximum core clock frequency.

HyperFlex Core Architecture in Stratix 10 Devices

Optimize Designs with the HyperFlex Architecture

The HyperFlex architecture enables three key design techniques to achieve 2X performance: Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization. Read the Stratix 10 High-Performance Design Handbook to learn how to combine these performance optimization techniques to achieve the highest clock frequencies in Stratix 10 devices.

Start Designing with the HyperFlex Architecture Today

The HyperFlex architecture leverages the Hyper-Aware design flow. This flow incorporates the innovative Fast Forward Compile feature that allows designers to perform rapid design performance exploration and attain breakthrough levels of performance.

Fast Forward Compile is available today, so you can start designing with the Stratix 10 HyperFlex architecture. Contact your sales representative to obtain a license.

Contact your local sales representative about evaluating Fast Forward Compile >>

Watch the Fast Forward Compile Demo Video

Watch this demo video about the Fast Forward Compile feature for Stratix 10 designs. This video shows you how the Fast Forward Compile feature provides innovative performance exploration capabilities and shows you how to implement the three key design optimizations for the HyperFlex architecture, including:

  • How to overcome retiming restrictions to enable Hyper-Retiming
  • How to optimize designs to implement Hyper-Pipelining
  • How to identify and overcome performance bottlenecks for Hyper-Optimization

Learn more about this unique capability on the Fast Forward Compile web page.

Register Now!

Register for Training on the HyperFlex Architecture

Intel® offers insructor-led training and online training courses covering design optimization techniques to extract the maximum performance from your design using the HyperFlex architecture.

Register now to schedule instructor-led training or to view free online training now.

Heterogeneous In-Package Integration

Stratix 10 FPGAs and SoCs leverage heterogeneous 3D system-in-package (SiP) technology to integrate a monolithic FPGA core fabric with 3D SiP transceiver tiles and other advanced components in a single package. Read the Enabling Next-Generation Platforms Using Intel's 3D System-in-Package Technology White Paper (PDF).

Scalable and Flexible Solutions

Heterogeneous 3D SiP integration enables a scalable and flexible path to deliver multiple product variants that mix functionality and/or process nodes effectively within a single package, meeting the system functionality requirements of today and those of the future.

Mixing Functionality and Process Nodes

Heterogeneous 3D SiP integration enables a number of major system-level benefits including:

  • High Performance: Heterogeneous integration provides a path to integrate higher bandwidth interface capabilities to meet the needs of 400 Gigabit to 1 Terabit systems.
  • Lower Power: Compared to discrete components on a PCB, heterogeneous integration reduces the amount of power spent on driving long interconnect to deliver an overall lower power solution.
  • Smaller Form Factor: By integrating discrete components in a single package, overall solution size can be decreased significantly including less board area used for routing.

Intel EMIB Packaging Technology for Stratix 10 devices

Intel’s patented Embedded Multi-Die Interconnect Bridge (EMIB) technology enables effective in-package integration of system-critical components, such as analog, memory, ASICs, CPU, and so on. EMIB technology offers a simpler manufacturing flow, compared to other in-package integration technologies.  Additionally, EMIB eliminates the need to use through silicon vias (TSV) and specialized interposer silicon enabling a solution that offers higher performance, less complexity, and superior signal and power integrity. EMIB uses a small silicon chip embedded in the substrate to provide ultra-high density interconnect between die. Standard flip chip assembly connects power and user signals from the chip to package balls. This approach minimizes interference from core switching noise and crosstalk thereby delivering superior signal and power integrity.

For details on the specific implementation of this technology on the upcoming Stratix 10 product family, see the Transceivers section.

Learn More about Heterogeneous 3D SiP Integration

Download this white paper to learn more about how Stratix 10 FPGAs and SoCs leverage heterogeneous 3D SiP integration to deliver performance, power, and form factor breakthroughs while providing greater scalability and flexibility. In addition, learn how Intel EMIB technology delivers a superior solution for multi-die integration.
 

Transceivers

Stratix 10 FPGAs and SoCs deliver a new era of transceiver technology with the introduction of innovative heterogeneous 3D system-in-package (SiP) transceivers. Transceiver tiles are combined with a monolithic programmable core fabric using system-in-pacakge integration to address ever increasing system bandwidth demands across virtually all market segments. Transceiver tiles enable the highest transceiver channel count FPGA without sacrificing ease-of-use.

Features

Transceiver Tile Variants

Stratix 10 Device Variants GX, SX GX, SX, TX, MX TX, MX
Transceivers per Tile 24 24 24

Maximum Chip-to-Chip Data Rates

NRZ

PAM-4

 

17.4 Gbps

         -


28.3 Gbps
        -

30 Gbps
56 Gbps

Maximum Backplane

Data Rates

NRZ
PAM-4


12.5 Gbps
        -

28.3 Gbps
        -

30 Gbps
56 Gbps
Insertion Loss at Maximum Data Rate Up to 18 dB Up to 30 dB Up to 30 dB
Hard IP

PCIe Gen1, 2, and 3 with x1, x4, x8, and x16 lane support

10G Fire Code FEC Hard IP

PCIe Gen1, 2, and 3 with x1, x4, x8, and x16 lanes 

SR-IOV with

4 Physical functions and

2K Virtual Functions

10G Fire Code FEC Hard IP

10/25/100 GbE MAC with RS-FEC

Heterogeneous 3D SiP Transceiver Advantages

Unprecedented Performance Highest Transceiver Count Family
  • Stratix 10 GX and SX devices support data rates up  to 28.3 Gbps, enabling mainstream protocols
  • Stratix 10 TX and MX devices support data rates up to 56 Gbps, enabling mainstream and future protocols including PAM-4 support
  • Up to 144 full duplex channels
  • Up to 6 Instances of PCI Express® (PCIe®) Gen3 with x16 hard IP
  • Hard IP support: 100GE MAC and PHY, RS-FEC
Flexibility and Scalability Ease of Use
  • Three different transceiver tiles capable of addressing the need of current and future protocol requirements
  • Dual-mode transceivers allows the switching between PAM-4 and NRZ modulation at data rates up to 56 Gbps
  • Adaptive continuous time-linear equalization (CTLE) and adaptive decision feedbacl equalization (DFE) addresses the need of long reach applications
  • Precision Signal Integrity Calibration Engine (PreSICE)
  • Both physical coding sublayer (PCS) and physical medium attachment (PMA) with dynamic reconfiguration capabilities

 Stratix 10 Transceiver Highlights

Features Capability

Chip-to-chip data rates

Versatile data rates supporting a variety of industry standards. Stratix 10  devices contain three channel types:

  • GX channels with data rates up to 17.4 Gbps
  • GXT channels with data rates up to 28.3 Gbps
  • GXE channels with data rates up to 56 Gbps

Backplane support

Drive backplanes, including 10GBASE-KR and 802.3bj compliance, at data rates up to 56 Gbps without external re-timers

Optical module support

SFP+/SFP, XFP, CXP, QSFP/QSFP28, CFP/CFP2/CFP4

Cable driving support

SFP+ Direct Attach, PCIe over cable, eSATA

Transmit pre-emphasis

Transmit pre-emphasis and de-emphasis to compensate for system channel loss

Adaptive Continuous Time-Linear Equalization (CTLE)

Adaptive linear equalization to compensate for system channel loss

Adaptive Decision Feedback Equalization (DFE)

Fully adaptive DFE to equalize backplane channel loss in the presence of crosstalk and noisy environments

Variable Gain Amplifier (VGA)

Broadband amplifier to maximize input dynamic range

Altera Digital Adaptive Parametric Tuning (ADAPT)

All digital adaptation engine to adjust all link equalization parameters automatically—including CTLE, DFE, and VGA blocks—providing optimal link margin without intervention from user logic

Precision Signal Integrity Calibration Engine (PreSICE)

Second-generation hardened calibration engine to calibrate all transceiver circuits quickly on power-up for optimal signal integrity performance

ATX Transmit Phased Locked-Loop (PLL)

Ultra-low jitter LC (inductor-capacitor) transmit PLL with continuous tuning range from 1 Gbps to 30 Gbps to cover a wide range of standards and proprietary protocols

Clock Mulitpler PLL (CMU PLL)

Ring oscillator-based transmit clock sources for multi-rate applications

Fractional PLL 

On-chip fractional frequency synthesizers to replace on-board crystal oscillators and reduce system cost

Digitally-Assisted Hybrid Clock-Data Recovery (CDR)

Superior jitter tolerance with fast lock time with independent channel PLL

On-Die Instrumentation—EyeQ and Jitter Margin Tool

Simplify board bring-up, debug, and diagnostics with non-intrusive, high-resolution eye monitoring (EyeQ)

PCIe Hard IP

Hardened PCIe Gen1, 2, 3 and with Gen3 x16 support, 100/25/10GE MAC and RS-FEC

External Memory Interfaces

Stratix 10 devices provide best-in-class memory interface support, including serial and parallel interfaces.

Serial Memory Interfaces

For serial memory, Intel supports next-generation, high-bandwidth interfaces including:

  • Hybrid Memory Cube (HMC)
    • HMC provides a significant increase in bandwidth relative to conventional solutions. The HMC specification has been developed by the Hybrid Memory Cube Consortium (HMCC). Intel is one of the leading members of the HMCC. For more details on Intel’s HMC solution, see the Hybrid Memory Cube page.
  • MoSys Bandwidth Engine or Mosys Bandwidth Engine2
    • Intel also supports other serial solutions, such as the MoSys bandwidth engine, which provide a solution for applications that require high transaction rates.

Parallel Memory Interfaces

Stratix 10 devices offer parallel memory support up to 2,666 Mbps for DDR4 SDRAM and supports a wide range of other protocols shown below.

  • Best-in-class hard memory controller delivers high-performance at low power including support for:
    • DDR4
    • DDR3 / DDR3L
    • LPDDR3
  • Soft controller support delivers flexibility to support a wide range of memory interface standards including:
    • RLDRAM 3
    • QDR II+ / QDR II + Xtreme / QDR IV

Secure Device Manager

The Stratix 10 device family introduces a new Secure Device Manager (SDM) available in all densities and device family variants. Serving as the central command center for the entire FPGA, the Secure Device Manager controls key operations, such as configuration, device security, single event upset (SEU) responses, and power management. The Secure Device Manager creates a unified, secure management system for the entire device, including the FPGA fabric, hard processor system (HPS) in SoCs, embedded hard IP blocks, and I/O blocks. Read the Stratix 10 Secure Device Manager Provides Best-in-Class FPGA and SoC Security White Paper (PDF).

Key Services Provided by the SDM

Key Operation Description
Configuration
  • Manages device startup in user mode
  • Supports loading user configuration data
  • Configuration  bitstream decompression
Security
  • Provides security services to other modules
  • Key encryption and authentication
  • Bitstream decryption
  • Tamper monitoring 
Single-Event Upset (SEU)
  • SEU detection and correction 
Power Management
  • Manages smart voltage ID operations
  • Monitors critical power supplies 

Secure Device Manager Key Benefits

User-Configurable Boot Process

With a dedicated processor managing configuration, Stratix 10 FPGA users can control the configuration order of the core logic in the FPGA or SoC. You can also select whether the FPGA design or the processor application boots up first, and whether the first system manages the configuration control of the second. The Secure Device Manager allows greater flexibility and user-selected configuration control compared to previous-generation FPGAs and SoCs.  

User-Scripted Response to SEU and Tamper Detection

You can control the FPGA or SoC responses to SEU and tamper detection, using a dedicated processor in the Secure Device Manager. Stratix 10 devices also support user-scripted device erasure, where reactive data zeroization serves a security response.

Physically Unclonable Function for Key Material and Identity

Stratix 10 devices enables user-access to a Physically Unclonable Function (PUF) that provides unique device fingerprinting for device identification, and serves as a secure key material for device encryption and authentication.

Anti-Tamper Protection

Stratix 10 devices include on-chip temperature sensors and device voltage rail monitors to detect tamper attacks on the FPGA or SoC. Additionally, the secure processor in the Secure Device Manager lets you  update the configuration process. You can deploy a different configuration order or updated encryption processes in the field if a particular configuration process is found to be ineffective against the threat profile.  

Advanced Key Management Schemes  

You can select different keys to encrypt various sections of the FPGA core (sectors). You can also design different key handling procedures for keys at different security or sensitivity levels. A key can be used across multiple sectors or a single sector to reduce the vulnerability of the entire design.

Additionally, you can update/retire/replace keys in the user key space and generate keys to include public and private key pairs within the FPGA or SoC; private keys are not revealed outside the Secure Device Manager.  

Comprehensive and Hardened Encryption and Authentication

Stratix 10 FPGAs and SoCs enable user-access to hard IP encryption and authentication accelerators. Supported accelerators include:

  • AES 256 Encrypt/Decrypt Accelerator
  • SHA2 256/384 Accelerator
  • ECDSA 256/384 Accelerator

You can use these accelerators for configuration and reconfiguration processes and user-defined encryption and authentication processes post-configuration.

Some hard IP encryption and authentication accelerators may be subject to appropriate user licensing.

Advanced Device Management

The user and command authentication capabilities of the Secure Device Manager also enable a whole class of new secure device maintenance functions for the Stratix 10 device family. These functions include:

  • Secure remote update (authenticated)
  • Secure return material authorization (RMA) of devices without revealing user keys
  • Secure debug of designs and ARM® code
  • Secure key management

Secure Device Manager Block Diagram

Learn More

Download this white paper to learn how the Secure Device Manager enable Stratix 10 FPGAs and SoCs to deliver a best-in-class security solution.

DSP

With Stratix 10 devices, digital signal processing (DSP) designs can achieve up to 10 tera floating point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations. This unprecedented degree of computational throughput is made possible by a hardened floating-point operators within each DSP block, initially introduced in the Arria® 10 device family, is extended to deliver an order of magnitude greater throughput in Stratix 10 FPGAs and SoCs. Read the Stratix 10 FPGA and SoC DSP backgrounder.

Download PDF Family table
 
Part # Reference

10SG050

10SX050
 

10SG065

10SX065

10SG085

10SX085

10SG110

10SX110

10SG165

10SX165
 

10SG210

10SX210

10SG250

10SX250

10SG280

10SX280

10SG450

10SX450

10SG550 

10SX550

Stratix 10 Product Line

GX 500

SX 500
 

GX 650

SX 650

GX 850

SX 850

GX 1100

SX 1100

GX 1650

SX 1650
 

GX 2100

SX 2100

GX 2500

SX 2500

GX 2800

SX 2800

GX 4500

SX 4500
 

GX 5500

SX 5500

Equivalent
LEs1
484,000 646,000 841,000 1,092,000 1,624,000 2,005,000 2,422,000 2,753,000 4,463,000 5,510,000
M20K Memory
Blocks
2,196 2,583 3,477 4,401 5,851 6,501 9,963 11,721 7,033 7,033
M20K Memory
(Mb)
43 50 68 86 114 127 195 229 137 137

Variable-Precision

DSP Blocks

1,152 1,440 2,016 2,520 3,145 3,744 5,011 5,760 1,980 1,980
18 x 19
Multipliers
2,304 2,880 4,032 5,040 6290 7,488 10,022 11,520 3,960 3,960

27 x 27

Multipliers

1,152 1,440 2,016 2,520 3,145 3,744 5,011 5,760 1,980 1,980
Fixed Point Performance (TMACS)2 4.6 5.8 8.1 10.1 12.6 15.0 20.0 23.0 7.9 7.9
Single Precision Floating Point Adders 1,152 1,440 2,016 2,520 3,145 3,744 5,011 5,760 1,980 1,980
Single Precision Floating Point Multipliers 1,152 1,440 2,016 2,520 3,145 3,744 5,011 5,760 1,980 1,980
Single Precision Floating Point (TFLOPS)3 1.8 2.3 3.2 4.0 5.0 6.0 8.0 9.2 3.2 3.2
Maximum User I/O Pins 488 488 736 736 704 704 1,160 1,160 1,640 1,640

Maximum 
Transceiver 
Count

24 24 48 48 96 96 144 144 72 72
Notes:
  1. LE counts valid in comparing across devices, and are conservative vs. competing FPGAs.
  2. Fixed-point performance assumes the use of of pre-adder.
  3. Floating-point performance is IEEE 754 compliant single precision.

 

Stratix 10 DSP Block: Standard-Precision Fixed-Point

Stratix 10 DSP Block: High-Precision Fixed-Point

Stratix 10 DSP Block: Single-Precision Floating Point

Unprecedented Performance

Stratix 10 devices deliver up to 23 TMACs of fixed-point performance and up to 10 TFLOPS of IEEE-754 single-precision floating-point performance

Breakthrough Peformance per Watt Efficiency

In addition to high performance, Stratix 10 devices can achieve power efficiency of up to 80 GFLOPS/Watt. This level of floating-point power efficiency is a signficant innovation for the floating-point processing industry delivering performance at a fraction of the power of alternative computing elements.

Optimized and Integrated Design Entry

Designing with floating-point operations is achievable via a number of design flows including:

Learn More About DSP in Stratix 10 FPGAs and SoCs

Learn about DSP block architecture in Stratix 10 FPGAs and SoCs and the productivity benefits of hardened floating-point DSP blocks by downloading the DSP backgrounder.

Learn more about designing filters for high performance using Stratix 10 devices.

SEU Mitigation

Single-event upsets (SEUs) are rare, unintended changes in the state of internal memory elements caused by radiation effects. The change in state results in a soft error and there is no permanent damage to the device.

Stratix 10 devices have intrinsically low upset rates as a result of the high SEU immunity provided by Intel's 14 nm Tri-Gate process. Additionally, Intel provides fine-grained capability for determining where an upset occurred in your design so you can design your system to have the appropriate response.

Stratix 10 FPGAs and SoCs ensure high reliability and provides best-in-class SEU mitigation capabilities.

  • Advanced SEU Detection (ASD)
    • Sensitivity processing
    • Hierarchy tagging
  • Fault injection
    • Use to characterize and improve your designs

Learn More:

Hard Processor System

Building on Intel’s leadership in SoCs, Stratix 10 SoCs include a next-generation hard processor system (HPS) to deliver the industry’s highest performance and most power-efficient SoCs. At the heart of the HPS is a highly efficient quad-core ARM* Cortex*-A53 processor cluster optimized for ultra-high performance per watt, which reduces power consumption up to 50% over previous-generation SoC FPGAs. Additionally, the HPS includes a System Memory Management Unit, Cache Coherency Unit, a hard memory controller, and a rich feature set of embedded peripherals. 

Quad-Core ARM Cortex-A53-Based HPS

Stratix 10 SoC Development Tools

The Intel SoC EDS featuring ARM Development Studio™ 5 (DS-5™) supports Stratix 10 SoCs, providing heterogeneous debug, profiling, and whole-chip visualization. The SoC EDS unifies all software debugging information from the CPU and FPGA domains and presents them in an organized fashion within the standard DS-5 user interface. The toolkit gives users an unprecedented level of debugging visibility and control that delivers substantial productivity gains.

To learn more, visit the Stratix 10 SoC page.