Stratix® II GX FPGAs are specifically architected to meet the full system demands of both current and future serial I/O-based applications. Stratix II GX devices fuse the industry's fastest and highest density FPGA architecture with up to 20 full-duplex, high-performance, multi-gigabit transceivers. The transceivers deliver excellent jitter performance across the entire 600-Mbps to 6.375-Gbps operating range. When used with the multiple levels of dynamic pre-emphasis and equalization, they provide a low-risk design path for both new system and legacy system design applications.
Table 1 highlights the features and benefits of Stratix II GX FPGA transceivers. Table 2 outlines Stratix II GX devices and features. Table 3 details the Stratix II GX transceiver, device packages, and maximum user I/O pins. Table 4 shows industrial temperature support for Stratix II GX FPGAs.
Table 1. Stratix II GX FPGA Transceiver Features Summary
|Excellent Signal Integrity||The transmitter has low jitter generation and up to 500 percent pre-emphasis. The receiver has excellent jitter tolerance, and up to 17-dB equalization, which can either be continuously and automatically adjusted by an on-chip controller, or set statically.|
|Low Power||The transceiver dissipates 225 mW per channel at 6.375 Gbps, and only 125 mW per channel at 3.125 Gbps.|
|PCS Support (Hard IP)||The transceiver supports the following PCS blocks: PCI Express, PIPE-Compliant PCS, CEI-6G-LR/SR, 8b/10b encoder/decoder, XAUI state machine and channel bonding, Gigabit Ethernet state machine, SONET, and 8b/10b and 8/10/16/20/32/40-bit interface (to FPGA logic).|
|System-Level Diagnostics||Serial loopback, reverse serial loopback, pseudo-random binary sequence (PRBS) generator and checker, and the registered-based interface facilitate dynamic reconfiguration of pre-emphasis, equalization, and differential output voltage.|
Table 2. Stratix II GX FPGA Features (1)
|Transceiver Data Rate||600 Mbps–6.375 Gbps|
|Adaptive Logic Modules (ALMs) (2)||13,552||24,176||36,384||53,016|
|Equivalent LEs (2)||33,880||60,440||90,960||132,540|
|M512 RAM Blocks||202||329||488||699|
|M4K RAM Blocks||144||255||408||609|
|Total RAM Bits||1,369,728||2,544,192||4,520,448||6,747,840|
|Embedded 18-Bit x 18-Bit Multipliers (3)||64||144||192||252|
|Availability||Buy Now||Buy Now||Buy Now||Buy Now|
- Features are preliminary and subject to change.
- Each ALM is equivalent to 2.5 LEs.
- Each DSP block in Stratix II GX devices can implement four 18×18 multipliers or one 36×36 multiplier. To obtain the total number of 36×36 multipliers per device, divide the total number of 18×18 multipliers by a factor of 4.
- Includes both enhanced PLLs and fast PLLs.
Table 3. Stratix II GX Transceiver, Device Packages, and Maximum User I/O Pins (1, 2)
|Device||Transceiver Channels||LVDS Channels||Device Package and User I/O|
|Receive||Transmit||F780 (29 mm) User I/O Pins||F1152 (35 mm) User I/O Pins||F1508 (40 mm) User I/O Pins|
- The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock-reference pins for high-speed I/O capability.
- User I/O counts are preliminary and subject to change.
- Includes two differential clock inputs that can also be used for two additional channels for the differential receiver.
Table 4. Stratix II GX Device Industrial Temperature Support
- View Webcast
- Download Software
- Get Training
- Get Design Example
- View Video
- Purchase Development Kits
- Purchase Devices
- Get Device Support
- View Knowledge Base
- Use Troubleshooter
- Join the Altera Forum
- Get Documentation
- Get Handbook (PDF)
- Get Data Sheet (PDF)
- Get Email Updates
- Get Product Catalog (PDF)
- Stratix II GX Transceiver Protocols
- Stratix II GX Signal Integrity Center
- Performance in High-Density FPGAs
- Benchmarking Methodology
- Stratix II GX Eye Diagram Viewer
- Stratix II GX Transceiver Overview