Stratix® II GX FPGAs are specifically architected to meet the full system demands of both current and future serial I/O-based applications. Stratix II GX devices fuse the industry's fastest and highest density FPGA architecture with up to 20 full-duplex, high-performance, multi-gigabit transceivers. The transceivers deliver excellent jitter performance across the entire 600-Mbps to 6.375-Gbps operating range. When used with the multiple levels of dynamic pre-emphasis and equalization, they provide a low-risk design path for both new system and legacy system design applications.

Table 1 highlights the features and benefits of Stratix II GX FPGA transceivers. Table 2 outlines Stratix II GX devices and features. Table 3 details the Stratix II GX transceiver, device packages, and maximum user I/O pins. Table 4 shows industrial temperature support for Stratix II GX FPGAs.

Table 1. Stratix II GX FPGA Transceiver Features Summary

Feature Description
Excellent Signal IntegrityThe transmitter has low jitter generation and up to 500 percent pre-emphasis. The receiver has excellent jitter tolerance, and up to 17-dB equalization, which can either be continuously and automatically adjusted by an on-chip controller, or set statically.
Low PowerThe transceiver dissipates 225 mW per channel at 6.375 Gbps, and only 125 mW per channel at 3.125 Gbps.
PCS Support (Hard IP)The transceiver supports the following PCS blocks: PCI Express, PIPE-Compliant PCS, CEI-6G-LR/SR, 8b/10b encoder/decoder, XAUI state machine and channel bonding, Gigabit Ethernet state machine, SONET, and 8b/10b and 8/10/16/20/32/40-bit interface (to FPGA logic).
System-Level DiagnosticsSerial loopback, reverse serial loopback, pseudo-random binary sequence (PRBS) generator and checker, and the registered-based interface facilitate dynamic reconfiguration of pre-emphasis, equalization, and differential output voltage.

Table 2. Stratix II GX FPGA Features (1)

Feature Device
EP2SGX30C/D EP2SGX60C/D/E EP2SGX90E/F EP2SGX130G
Transceiver Data Rate600 Mbps–6.375 Gbps
Adaptive Logic Modules (ALMs) (2)13,55224,17636,38453,016
Equivalent LEs (2)33,88060,44090,960132,540
LVDS Channels29294578
M512 RAM Blocks202329488699
M4K RAM Blocks144255408609
M-RAM Blocks1246
Total RAM Bits1,369,7282,544,1924,520,4486,747,840
DSP Blocks16364863
Embedded 18-Bit x 18-Bit Multipliers (3)64144192252
PLLs (4)44/4/888
AvailabilityBuy NowBuy NowBuy NowBuy Now

Notes:

  1. Features are preliminary and subject to change.
  2. Each ALM is equivalent to 2.5 LEs.
  3. Each DSP block in Stratix II GX devices can implement four 18×18 multipliers or one 36×36 multiplier. To obtain the total number of 36×36 multipliers per device, divide the total number of 18×18 multipliers by a factor of 4.
  4. Includes both enhanced PLLs and fast PLLs.

Table 3. Stratix II GX Transceiver, Device Packages, and Maximum User I/O Pins (1, 2)

Device Transceiver Channels LVDS Channels Device Package and User I/O
Receive Transmit F780 (29 mm) User I/O Pins F1152 (35 mm) User I/O Pins F1508 (40 mm) User I/O Pins
EP2SGX30C43129361
EP2SGX60C43129364
EP2SGX30D83129361
EP2SGX60D83129364
EP2SGX60E1242 (3)42534
EP2SGX90E1247 (3)45558
EP2SGX90F1659 (3)59650
EP2SGX130G2073 (3)71734

Notes:

  1. The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock-reference pins for high-speed I/O capability.
  2. User I/O counts are preliminary and subject to change.
  3. Includes two differential clock inputs that can also be used for two additional channels for the differential receiver.

Table 4. Stratix II GX Device Industrial Temperature Support

Device Package Speed Grade
EP2SGX30D780-pin FBGA-4
EP2SGX60D780-pin FBGA-4
EP2SGX60E1,152-pin FBGA-4
EP2SGX90E1,152-pin FBGA-4
EP2SGX90F1,508-pin FBGA-4
EP2SGX130G1,508-pin FBGA-4

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