Stratix II GX Physical Coding Sub-Layer

The Stratix® II GX transceiver FPGAs include specific digital functionality to deliver physical coding sub-layer compliance for a number of key protocols used in backplane, line card, and chip-to-chip applications. The blocks are optimized for enhanced protocol support, reducing the amount of resources required in the FPGA to implement the physical layer of the protocol, while maintaining a low-power solution. The blocks, when combined with specific intellectual property (IP) and reference designs, can provide a complete protocol solution, both simplifying potentially complex designs and reducing project risk. Table 1 shows the key protocols supported by Stratix II GX transceiver FPGAs.

Table 1. Stratix II GX Protocol Support

Protocol Data Rate Complete Solution
PCI-Express 1.12.5 GbpsIP
SDH/SONET OC-12622 Mbps-
SDH/SONET OC-482.488 Gbps-
Gigabit Ethernet (GbE)1.25 GbpsIP
10-Gigabit Ethernet XAUI 3.125 GbpsIP
SD-SDI270 Mbps (1)Reference Design
HD-SDI1.488 GbpsReference Design
SerialLite II622 Mbps – 6.375 GbpsIP
Serial RapidIOTM1.25 Gbps, 2.5 Gbps, 3.125 GbpsIP
OIF CEI-6LR/SR6.25 GbpsReference Design


  1. Data rate supported using oversampling

Physical Coding Sublayer Block

The physical coding sublayer (PCS) block simplifies protocol support by including specific hard logic within the transceiver. Figure 1 shows a block implementation of the Stratix II GX PCS architecture.

Figure 1. Stratix II GX PCS Architecture

Figure 1. Stratix II GX PCS architecture
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The Stratix II GX PCS provides key features to deliver protocol compliance within the transceiver block. In addition, dedicated state machines are included to support the PCI Express, GbE, and XAUI protocols. The state machines both configure and control the various PCS sub-blocks to support the specified protocol, further simplifying implementation. Tables 2 and 3 show PCS support by protocol.

Table 2. PCS Implementation by Protocol (8b/10b Encoding)

Required PCS Functions PCI Express
(Gen. 1)
GbE XAUI Serial RapidIO SerialLite II
Data Rates (Gbps) – 6.375
Channel Bonding1, 4, 8141, 4up to x16
Possible Reference Clock Values (MHz)100125156.25156.2562.2-622.08
FPGA Bus Width (bits)8 or 16816168, 10, 16, 32
Dedicated Sync State MachineCheckCheckCheck
Word AlignCheckCheckCheckCheckCheck
Rate MatchCheckCheckCheckCheck
Byte Serialize/DeserializeCheck CheckCheckCheck
Phase Comp FIFO BufferCheckCheckCheckCheckCheck
Byte Re-Ordering
Single Bit Slip Check
Special InterfacePIPE-1.0GMII Like (2)XGMII Like (3)

Table 3. PCS Implementation by Protocol (Scrambled Encoding)

Required PCS Functions CEI-6G SDH/SONET Scrambled Backplane SD-SDI HD-SDI
Data Rates (Gbps)6.3750.6222.4880.270 (1)1.485
Channel Bonding11111
Possible Reference Clock Values (MHz)155.52 - 622.0862.2, 311.0477.76, 155.52, 311.04, 622.0867.574.25
FPBA Bus Width (bits)328161010
Word Align CheckCheckCheckCheck
Rate Match
Byte Serialize/DeserializeCheck Check
Phase Comp FIFO BufferCheckCheckCheckCheckCheck
Byte Re-Ordering Check
Single Bit SlipCheck

Notes to Tables 2 and 3:

  1. Data rate achieved by oversampling
  2. GMII support for Gigabit Ethernet only
  3. XGMII has SDR instead of DDR interface

Each block within the transceiver is highly configurable to support both industry standard and customer proprietary protocols. Transceiver implementation is simplified within the Quartus® II development tool. The tool automatically configures the transceiver PCS block, to the support the selected protocol, speeding up implementation and reducing design risk. The development tools also provide basic configuration modes for proprietary and non-standard protocols.

Built-In Self Test (BIST)

The BIST provides a powerful set of diagnostic capabilities to the transceiver. It includes a pattern generator and checker for pseudo-random binary sequence (PRBS) and others. The BIST also features four loopback configurations that can be used for system diagnostics, allowing interrogation of the physical media attachment (PMA), the PCS, or both the PMA and PCS layers of the transceiver into the FPGA.