Stratix II GX FPGA Transceiver Protocols

It has become commonplace to use transceiver-based architecture to meet increased data bandwidth requirements in many applications. A number of protocols have emerged to support these applications and are now industry standards.

The Stratix® II GX FPGA transceiver architecture greatly simplifies protocol implementation by adding dedicated functionality within the physical coding sublayer block of the transceiver to meet compliance. The transceiver has been specifically designed to support the widest possible range of protocol standards across multiple data rates, while offering excellent signal integrity and keeping power consumption low.

Figure 1 shows Stratix II GX FPGA key protocol support by typical application.

Figure 1. Key Protocols & Applications

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Stratix II GX FPGAs support a complete solution for protocol-based applications. The solution includes dedicated intellectual property (IP) cores, development boards, reference designs, collateral, and protocol-specific characterization reports. The solutions, combined with Quartus® II development tools and SOPC Builder, help to reduce development overhead in both FPGA resources and engineering efforts.

Table 1 shows key protocol data rates and solution packages.

Table 1. Stratix II GX Complete Protocol Solutions

Standards Data Rate Complete Solution
Number of
Channels in Link
IP Kit Characterization
PCI Express2.5 Gbps1,4,8CheckCheckCheck
PCI Express 2.05.0 Gbps1,4,8 Check
CEI-6G6.375 Gbps1 CheckCheck
SONET OC-12622 Mbps1 CheckCheck
SONET OC-482.488 Gbps1 CheckCheck
Gigabit Ethernet1.25 Gbps1CheckCheckCheck
10 Gigabit Ethernet XAUI3.125 Gbps4CheckCheckCheck
SD-SDI270 Mbps1 CheckCheck
HD-SDI1.485 Gbps1 CheckCheck
3G-SDI2.97 Gbps1Check Check
Serial RapidIO® (SRIO) Standard3.125 Gbps1,4Check Check
Fibre Channel1.0625, 2.125, 4.25 Gbps1Check Check
SerialLite II622 Mbps – 6.375 Gbps1-256CheckCheckCheck
CPRI0.614, 1.228, 2.4576 Gbps1 Check
GPON1.24416 Gbps1 Check