It has become commonplace to use transceiver-based architecture to meet increased data bandwidth requirements in many applications. A number of protocols have emerged to support these applications and are now industry standards.
The Stratix® II GX FPGA transceiver architecture greatly simplifies protocol implementation by adding dedicated functionality within the physical coding sublayer block of the transceiver to meet compliance. The transceiver has been specifically designed to support the widest possible range of protocol standards across multiple data rates, while offering excellent signal integrity and keeping power consumption low.
Figure 1 shows Stratix II GX FPGA key protocol support by typical application.
Figure 1. Key Protocols & Applications
Stratix II GX FPGAs support a complete solution for protocol-based applications. The solution includes dedicated intellectual property (IP) cores, development boards, reference designs, collateral, and protocol-specific characterization reports. The solutions, combined with Quartus® II development tools and SOPC Builder, help to reduce development overhead in both FPGA resources and engineering efforts.
Table 1 shows key protocol data rates and solution packages.
Table 1. Stratix II GX Complete Protocol Solutions
|Standards||Data Rate||Complete Solution|
Channels in Link
|PCI Express||2.5 Gbps||1,4,8|
|PCI Express 2.0||5.0 Gbps||1,4,8|
|SONET OC-12||622 Mbps||1|
|SONET OC-48||2.488 Gbps||1|
|Gigabit Ethernet||1.25 Gbps||1|
|10 Gigabit Ethernet XAUI||3.125 Gbps||4|
|Serial RapidIO® (SRIO) Standard||3.125 Gbps||1,4|
|Fibre Channel||1.0625, 2.125, 4.25 Gbps||1|
|SerialLite II||622 Mbps – 6.375 Gbps||1-256|
|CPRI||0.614, 1.228, 2.4576 Gbps||1|