Differences Between Stratix II & Stratix II GX Devices

Stratix® II GX 90-nm devices combine the industry's highest density and fastest FPGA architecture with a new generation of transceivers to provide a balanced solution for the growing number of applications and protocols requiring high-speed transceiver I/O circuitry. Stratix II GX FPGA fabric is built on the Stratix II FPGA architecture and includes the adaptive logic module (ALM), digital signal processing (DSP) blocks, design security, and source-synchronous I/O circuitry with dynamic phase alignment (DPA) supporting data rates up to 1Gbps.

Transceiver Blocks

The transceivers have been architected to reduce the complexity of high-speed system design and offer excellent jitter performance. Added technology compensates for board layout losses, meaning the transceiver can be used in both new and legacy systems. The transceiver block also includes key features, making it simpler to implement a number of protocols including PCI Express, Common Electrical Interface 6-Gbps (CEI-6G), serial digital interface (SDI), XAUI, Serial RapidIOTM standard, SONET, Gigabit Ethernet, and SerialLite II. There are a range of Stratix II GX devices with up to 20 transceivers operating between 600 Mbps and 6.375 Gbps, meeting the requirements of many of today’s high-speed applications while maintaining excellent signal integrity performance.

FPGA Architecture

Stratix II GX silicon architecture effectively takes the Stratix II base device and replaces one side of the device I/O circuitry with high-speed transceivers; all other key features of the Stratix II FPGA remain. Figure 1 provides a simplistic view of the Stratix II GX I/O bank configuration.

Figure 1. Stratix II GX I/O Bank Configuration

The integration between the FPGA and transceiver is carefully designed to manage device signal integrity, simultaneous switching noise (SSN), and jitter transfer between the FPGA and transceiver portion of the device. Table 1 summarizes the FPGA features offered by Stratix II and Stratix II GX devices.

Table 1. Stratix II and Stratix II GX Feature Comparison

Features Device
Stratix II Stratix II GX
90-nm SRAM Process Technology (1)Check MarkCheck Mark
1.2-V Core Voltage (1)Check MarkCheck Mark
ALM Structure (1, 2)Up to 179,400 equivalent LEs (3)Up to 132,540 equivalent LEs
TriMatrix Memory (1)Up to 9 Mbits of memoryUp to 6.7 Mbits of memory
Embedded Multipliers (1)Up to 384 18x18 multipliersUp to 252 18x18 multipliers
Enhanced & Fast PLLs (1, 4, 5)Check MarkCheck Mark
External Memory Interface Support Including DDR2, RLDRAM II, QDR II, DDR, QDR, SDR (1)Check MarkCheck Mark
Source-Synchronous Signaling With Dynamic Phase Alignment (1)Up to 156 channels running at 1GbpsUp to 78 channels running at 1Gbps
Design Security (1)Check MarkCheck Mark


  1. These features are functionally identical in Stratix II and Stratix II GX devices.
  2. ALM = adaptive logic module
  3. LEs = logic elements
  4. PLLs = phase-locked loops
  5. The number of enhanced and fast PLLs are not identical in Stratix II and Stratix GX devices; Stratix GX devices also feature PLLs in the transceiver blocks.

Stratix II GX devices offer a subset of the densities offered by the Stratix II devices, as shown in Table 2. For devices of equivalent densities, the Stratix II GX device offers fewer enhanced and fast PLLs because the transceiver blocks contain internal dedicated transmitter and receiver PLLs. Stratix II GX devices are offered in different package and pin-out configurations than Stratix II devices, and are optimized for multigigabit operation.

Table 2. Stratix II and Stratix II GX Density Comparison

Stratix II Stratix II GX
Device Equivalent LEs Source-
Channels (1)
PLLs Device Equivalent LEs Transceiver Channels Source-
Channels (1)
PLLs (2)
Receive Transmit
EP2SGX60E60,4401242 (3)428
EP2S9090,96011812EP2SGX90E90,9601245 (3)458
EP2SGX90F90,9601659 (3)598
EP2S130132,54015612EP2SGX130G132,5402073 (3)718


  1. Channel count will vary with package. The Stratix II Device Family Data Sheet (PDF) and the Stratix II GX Device Data Sheet (PDF) contain more information and details.
  2. Only enhanced and fast PLLs are included here; transceiver PLLs are not listed.
  3. Includes two differential clock inputs that can also be used for two additional channels for the differential receiver.