What speed grades will be available?
Stratix II GX devices will be available in three speed grades: -3, -4, and -5, with -3 being the fastest and -5 the slowest.
What is the remote system upgrade feature?
The remote system upgrade feature allows you to reconfigure Stratix II GX devices from a remote source, extending your product’s lifespan while also saving time and costs. New configuration data can be sent to a system from a remote source, saved to an external memory device such as an advanced configuration device, and subsequently used to reconfigure the Stratix II GX device. If an error occurs during this process, the devices automatically initiate re-configuration from the external memory device using safe, default factory-configured settings.
What is the design security feature in Stratix II GX FPGAs?
Stratix II GX devices use the advanced encryption standard (AES) algorithm with a 128-bit key to encrypt the configuration bitstream. Selected by the National Institute of Standards and Technology (NIST) and adopted by the United States government to protect sensitive information, AES is the most advanced encryption algorithm available today. Other FPGA vendors support triple data encryption standard (triple DES) bitstream encryption using a battery to power-up or back-up the volatile key. Such approaches are very difficult to implement, increasing board-level concerns regarding possible system malfunctions and the need for redundancy. When the battery fails in the field, for example, the FPGA will not power on, causing the board to malfunction. Stratix II GX devices simplify system design by eliminating the need for a constant power source. Stratix II GX devices support the best configuration bit stream encryption available in the FPGA market.
When did Stratix II GX devices become available?
Engineering samples of the first Stratix II GX device, the EP2S90GX, were made available in Q1 2006, and the remaining Stratix II GX devices rolled out over the following six months.
What is the process technology for Stratix II GX devices?
Stratix II GX devices are based on the 1.2-V, 90-nm, nine-layer-metal, all-layer-copper process technology from TSMC. This extends the process-leadership advantages Altera gained when rolling out the Stratix II and Cyclone® II families, now in production. Stratix II GX devices use a low-k dielectric and are manufactured on 300-mm wafers.
What is the volume price for Stratix II GX devices?
Pricing for Stratix II GX devices is dependent on the density, package, performance, and volume quantities of the devices ordered. Typically, Stratix II GX pricing will be lower than using the equivalent Stratix II device with an external transceiver. Please contact your Altera sales representative or distributor for more specific pricing information.
Why did Altera announce Stratix II GX FPGAs before silicon was ready?
Altera customers have stated they prefer to start high-density FPGA software design before they have the actual devices. Advanced knowledge of the features and functions of the Stratix II GX devices allowed system architects and designers to begin implementing the transceiver as well as the logic functionality of their next-generation systems. Designers were also able to start developing their Stratix II GX FPGA designs using HSPICE simulation models, optimized Stratix II GX device IP functions (such as PCI Express and SerialLite II) and Altera’s Quartus® II development software version 5.1 right away.
What software is available to support Stratix II GX devices?
Stratix II GX devices are fully supported by Quartus II design software version 5.1 and beyond. In addition to Stratix II GX device compilation support, Quartus II version 5.1 software offers a host of new features, including advanced timing closure capabilities, the SignalTap® II logic analyzer, and formal verification support.
Which third-party tools will support Stratix II GX devices?
In addition to the Quartus II integrated synthesis tool, synthesis and simulation tools from leading EDA vendors Cadence, Mentor Graphics®, Synopsys, and Synplicity all support Stratix II GX devices, ensuring the highest quality of results in Altera FPGAs.
Which IP cores will be available for Stratix II GX devices?
All IP cores currently available for Stratix II FPGAs will be available for Stratix II GX devices.
New IP cores for implementing I/O protocols using the embedded transceiver blocks are available from Altera and Altera Megafunction Partner Program (AMPPSM) partners including:
- PCI Express
- 10 Gigabit Ethernet Media MAC
- 10 Gigabit Ethernet PCS
- 1 Gigabit Ethernet MAC
- SONET Framer
- SerialLite II
Transceiver-based IP cores leverage the dedicated functional blocks within each transceiver channel for an easy-to-use solution for complex applications. Additional functionality and higher-level processing is implemented in the general programmable logic resources within the device.
Can Nios II embedded processors be used with Stratix II GX devices?
Yes, the advanced architectural features of Stratix II GX devices combined with the Nios II family of embedded processors offer unparalleled processing power to meet the needs of network, telecommunications, DSP applications, mass storage, and other high-bandwidth systems.
For answers to your technical questions, please visit the Altera Find Answers section.