Lowest Power High-End 65 nm FPGA
To design the Stratix III FPGA, Altera's product planners began with the Stratix II FPGA architecture. Then, in collaboration with the top technologists from over 50 of Altera's major customers, they defined, designed, and developed the most advanced FPGA architecture for next-generation systems.
As a result, the Stratix III 65 nm FPGA incorporates features to combine high performance with the lowest possible static and dynamic power consumption—up to 50 percent lower than previous generation high-end FPGAs, including:
The Stratix III FPGA family is engineered for high-speed core performance, coupled with high-speed I/O and the best signal integrity in the industry. For example, they are the only 65 nm FPGA family capable of implementing DDR3 at 533 MHz and to offer LVDS performance up to 1.6 Gbps. This increase in performance is achieved by the implementation of:
Best Price/Performance Options
To give you the best price/performance solution for your design applications, Altera's Stratix III FPGA family offers two application-optimized variants:
- Stratix III L devices focus on logic-rich applications
- Stratix III E devices focus on DSP-rich and memory-rich applications
There are also migration paths between all members of the Stratix III FPGA family and the Stratix IV E FPGA. See the Migrate Your Stratix III FPGA Designs Up to a Stratix IV E FPGA Without Changing Pin-Outs page for details.
Advanced Process Technology
Altera and long-standing fabrication partner the Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), have been working on 65 nm process technologies since 2003. Since then, Altera has developed multiple test chips as part of a rigorous program to ensure that Stratix III FPGAs are on the latest 65 nm technology, and continue to be successfully delivered in volume and on schedule.
Exceed Performance and Finish Faster
Altera’s Quartus II software gives you the development and productivity tools you need to complete development faster and ensure you have the performance, power, and signal integrity needed to meet or exceed your design requirements.
- Timing Analyzer—supports industry-standard Synopsys Design Constraints (SDC)-based timing analysis methodology to complete timing closure quickly
- Incremental Compilation—supports team-based design, providing faster compilation for design iterations while preserving performance
- PowerPlay Power Analysis and Optimization Technology—provides automated power optimization to manage power from design concept through implementation
- Four-Stage Signal Integrity Analysis—provides optimal design performance