Stratix V FPGA Applications

Stratix V FPGAs address the design challenges for applications in a variety of industries. Expand the sections below for details about specific applications.

  • Multi-standard client interfaces enabled through easy-to-use partial reconfiguration and serial transceivers with continuous data range of 600 Mbps to 14.1 Gbps
  • Enhanced clocking flexibility with up to 44 independent transmit clock domains
  • Integrated electronic dispersion compensation (EDC) capability in transceivers to enable direct drive of optical modules (SFP+, SFP, QSFP, CFP)
  • 28.05-Gbps transceivers for next-generation optical interfaces
  • Advanced fPLL replacing external voltage-controlled crystal oscillators (VCXOs)
  • Higher system integration through highest density and hard PCS blocks for 40 GbE, 100 GbE, and Interlaken
  • High-bandwidth data-buffering with up to 1,600-Mbps external memory interfaces
  • Efficient implementation of packet processing and traffic management functions
  • Higher system performance while staying within your power and cost budget
  •  Highest bandwidth through 66 identical transceivers with continuous data rate from 600 Mbps to 14.1 Gbps
  • Built-in advanced signal conditioning circuitry for direct drive of 10GBASE-KR backplanes
  • Flexible support for various line-card interfaces with partial and dynamic reconfiguration
  • Optimized implementation of scheduling functions through high level of integration
  • Efficient floating-point multiplication with over 1.25 TFLOPS
  • Higher signal processing bandwidth with up to 2.5 TMACS
  • Automatic single event upset (SEU) detection and correction
  • Design security with enhanced Advanced Encryption Standard (AES) algorithm and 256-bit volatile and non-volatile keys
  • Productivity-boosting tools in Quartus® Prime software, including DSP Builder Advanced Blockset and incremental compilation
  • Reduced board space, power, and cost via fewer data channels and higher throughput per channel
  • Lower system latency and increased system performance and reliability via greater integration
  • Design differentiation using highest DSP- and memory-to-logic ratios
  • Higher multiple-input multiple-output (MIMO) and bandwidth density compared to competitive offering

 

  • Best-in-class serial digital interface (SDI) solution
  • Support for multiple CODECs through user-friendly partial reconfiguration
  • Optimal memory design with native 10-bit support
  • Efficient video processing with high multipliers-and memory-to-logic ratios
  • Complete solution via CODECs and 1080p video framework IP core