Altera's 28 nm Stratix® V FPGAs deliver the industry's highest bandwidth, highest level of system integration, and ultimate flexibility with reduced cost and the lowest total power for high-end applications.

Attain Breakthrough Bandwidth with Power-Efficient Transceivers

  • Integrated 28.05- and 14.1-Gbps transceivers, with up to 50 percent lower transceiver power compared to previous-generation devices
  • Up to 6 x72 DDR3 memory interfaces at 933 MHz
  • 2.5 TMACS of signal processing performance
  • PCI Express® Gen3, Gen2, and Gen1 hard intellectual property (IP) support
  • Embedded HardCopy® Blocks and integrated hard IP in the core and transceivers, which harden critical datapath components to eliminate system bottlenecks

Achieve Higher Integration on a Single Chip and Reduce Your Costs

  • Double the density without a cost and power penalty, through Embedded HardCopy Blocks, which deliver up to 14.3M ASIC gates or up to 1.19M logic elements. The blocks harden standard or logic-intensive functions including interface protocols like PCI Express Gen3, Gen2, and Gen1, and application-specific functions like 40G/100G/400G.
  • Partial reconfiguration, which enables you to reduce the size of FPGAs, saving board space, cost, and power
  • Fractional phase-locked loops (fPLLs), which provide increased clocking flexibility and replace on-board voltage-controlled crystal oscillators (VCXOs)
  • Integrated electronic dispersion compensation (EDC) capability in transceivers, which eliminates the need for external PHY to interface to optical modules

Get Ultimate Flexibility for Your Designs

  • User-friendly fine-grain partial reconfiguration, which allows you to change core functionality on the fly
  • Dynamically reconfigurable transceivers, which let you easily support multiple protocols, data rates, and physical media attachment (PMA) settings
  • Configuration via Protocol (CvP) using the existing PCI Express link in your application, which allows for a less complex board design

Lower Your System Power

Stratix V FPGAs reduce total power by 30 percent compared to previous-generation devices through key technologies:

  • Programmable Power Technology which maximizes core performance while simultaneously reducing power
  • TSMC's 28-nm high-K metal gate high-performance process optimized for lower power
  • 0.85-V/0.9-V core voltage
  • Partial reconfiguration
  • Embedded HardCopy Blocks and integrated core and transceiver hard IP

Table 2. Comparison of Stratix V Variants

Feature Stratix V E
Stratix V GS
Stratix V GX
Stratix V GT
High-Performance Adaptive Logic Modules (ALMs) 359,200 262,400 359,200 234,720
Variable-Precision DSP Blocks (18x18) 704 3,926 798 512
M20K Memory Blocks 2,640 2,567 2,660 2,560
External Memory Interface        
Partial Reconfiguration        
Fractional Phase-Locked Loop (PLL)        
Design security        
Single Event Upset (SEU) Mitigation        
PCI Express® Gen3, Gen2, Gen1 Hardened IP Block(s) - Up to 4 Up to 4 1
Embedded Hard IP Blocks -      
Transceivers (1) - 14.1 Gbps / 48 14.1 Gbps / 66 28.05 Gbps / 4
12.5 Gbps / 32

1. Data rate / number of transceiver channels.

Family Overview Table

Listing of All Device Variations