Stratix FPGA discontinued June 1st, 2017

Stratix FPGAs are available in the following variations:

  • Stratix FPGAs provide up to 80K logic elements (LEs) and 7.3 Mbits of on-chip RAM arranged in TriMatrix memory blocks, operating at up to 350 MHz.
  • Stratix GX FPGAs were the first programmable logic devices to incorporate high-speed serial transceivers operating at multi-gigabit speeds.

Stratix Architecture

Stratix Device Features

Feature Description
High-Performance Architecture
High-Performance Architecture The high-performance Stratix device architecture consists of a speed-optimized interconnect and a highly efficient clock network that provide connectivity between logic elements (LEs), TriMatrix memory blocks, digital signal processing (DSP) blocks, phase-locked loops (PLLs), and I/O elements (IOEs) to maximize system performance. Designers requiring higher performance can use Stratix II FPGAs.
Up to 79,040 LEs and up to 7 Mbits of Embedded Memory The high device density of Stratix FPGAs and embedded memory complement the bandwidth and performance of the Stratix device architecture. Designers requiring higher density can use Stratix II FPGAs.
High Memory Bandwidth and High-Speed External Memory Interfaces
TriMatrix Memory TriMatrix memory offers up to 7 Mbits of RAM and 8 terabits per second of device memory bandwidth. This complex memory structure includes three sizes of embedded RAM blocks—M512, M4K, and M-RAM blocks—that can be configured to support a wide range of applications.
External Memory Interfaces Stratix FPGAs provide advanced external memory interfaces, allowing designers to integrate external high-density SRAM and DRAM devices into complex system designs without degrading data access performance.
SRAM Devices Stratix FPGAs support interfaces with three types of SRAM devices—double data rate (DDR), quad data rate (QDR), QDRII, and zero bus turnaround (ZBT)—at up to 200 MHz.
DRAM Devices Stratix FPGAs support interfaces with three types of high-speed synchronous DRAM (SDRAM) devices: single data rate (SDR SDRAM), DDR SDRAM, and fast-cycle (FCRAM) with up to a 200-MHz clock.
High-Performance DSP
DSP Blocks Stratix FPGAs include high-performance embedded DSP units that are optimized for DSP applications. The DSP blocks eliminate performance bottlenecks in DSP applications, provide predictable and reliable performance, and result in resource savings without compromising performance.
DSP Performance Stratix FPGAs offer higher data processing capacity than DSP processors for maximum system performance.
Soft Multipliers Stratix FPGAs provide a flexible implementation of soft multipliers that can be configured for different data width and latency. The soft multipliers provide very high DSP throughput in addition to the DSP blocks.
High I/O Bandwidth and High-Speed Interfaces
High I/O Bandwidth With support for a variety of single-ended and differential I/O standards, Stratix devices easily interface with backplanes, host processors, buses, memory devices, and 3D graphics controllers.
Differential I/O Support The Stratix True-LVDS circuitry offers up to 152 high-speed differential I/O channels with up to 80 channels optimized for data rates up to 840 Mbps. It also addresses the high-performance needs of emerging I/O interfaces, including support for the LVDS, LVPECL, PCML, and HyperTransport™ standards.
Single-Ended I/O Support Stratix FPGAs support high-bandwidth single-ended I/O interface standards, such as SSTL, HSTL, GTL, GTL+, CTT, and PCI-XTM, needed for today's demanding system requirements.
High-Speed Interfaces Stratix FPGAs support a wide array of high-speed interface standards, such as the SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, HyperTransport, RapidIO®, and UTOPIA IV standards, for flexibility and fast time-to-market.
System Clock Management
Clock Management Circuitry Stratix FPGAs feature up to 12 programmable PLLs and 40 system clocks, providing robust clock management and frequency synthesis capabilities for maximum system performance.
Clock Management Features Stratix PLLs offer features previously found only in high-end discrete PLL devices, including clock switchover, PLL reconfiguration, spread-spectrum clocking, frequency synthesis, programmable phase shift, programmable delay shift, external feedback, and programmable bandwidth. These features allow designers to manage system timing on and off the Stratix FPGA.
Automatic Cyclic Redundancy Code (CRC) Checking
CRC Stratix FPGAs feature automatic 32-bit CRC checking. A single click in Quartus® II version 4.1 software simplifies setup and activates the device's built-in CRC checker. It is the most cost-effective FPGA solution available for single event upset (SEU).
On-Chip Hot-Socketing and Power-Sequencing Support
Hot Socketing and Power Sequencing Stratix FPGAs offer robust on-chip hot-socketing and power-sequencing support that ensures proper device operation independent of the power-up sequence. This feature also protects the device and tri-states I/O buffers before and during power up, making Stratix FPGAs ideal for multi-voltage systems as well as for applications that require high availability and redundancy.
Remote System Upgrade Capabilities
Remote System Upgrades Stratix FPGAs feature a remote system upgrade capability, allowing secure, reliable, error-free deployment of system upgrades from a remote location.
Embedded Processor Cores
Nios II Family of Embedded Processors The advanced architectural features of Stratix FPGAs combined with Nios® II embedded processors offer unparalleled processing power to meet the needs of networks, telecommunications, DSP applications, mass storage, and other high-bandwidth systems. Stratix FPGAs improve the performance of Nios II processors to over 150 DMIPS.
Feature EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
LEs 10,570 18,460 25,660 32,470 41,250 57,120 79,040
M512 RAM Blocks
(512 Bits + Parity)
94 194 224 295 384 574 767
M4K RAM Blocks
(4 Kbits + Parity)
60 82 138 171 183 292 364
M-RAM Blocks
(512 Kbits + Parity)
1 2 2 4 4 6 9
Total RAM Bits 920,448 1,669,248 1,944,576 3,317,184 3,423,744 5,215,104 7,427,520
DSP Blocks 6 10 10 12 14 18 22
9-Bit x 9-Bit Embedded Multipliers (1) 48 80 80 96 112 144 176
PLLs 6 6 6 10 12 12 12
Maximum User I/O Pins 426 586 706 726 822 1,022 1,203
Availability Buy Now Buy Now Buy Now Buy Now Buy Now Buy Now Buy Now
Notes:
  1. Total number of 9 x 9 multipliers. To obtain the total number of 18 x 18 multipliers per device, divide the total number of 9 x 9 multipliers by a factor of 2. To obtain the total number of 36 x 36 multipliers per device, divide the total number of 9 x 9 multipliers by a factor of 8.
Package Size
(mm x mm)
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
672-Pin BGA
35 x 35
345 426 473 - - - -
956-Pin BGA
40 x 40
- - - 683 683 683 683
484-Pin FineLine BGA
23 x 23
335 361 - - - - -
672-Pin FineLine BGA
27 x 27
345 426 473 - - - -
780-Pin FineLine BGA
29 x 29
426 586 597 597 615 - -
1,020-Pin FineLine BGA
33 x 33
- - 706 726 773 773 773
1,508-Pin FineLine BGA
40 x 40
- - - - 822 1,022 1,203
Configuration Device Number of Devices
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
EPC2 3 4 5 7 8 11 15
EPC4 1 1 - - - - -
EPC8 1 1 1 1 1 - -
EPC16 1 1 1 1 1 1 1
Device Package Speed Grade
EP1S10 484-pin FBGA
672-pin FBGA
780-pin FBGA
-6
-7
-6
EP1S20 484-pin FBGA
672-pin FBGA
780-pin FBGA
-6
-7
-6
EP1S25 672-pin FBGA
780-pin FBGA
1,020-pin FBGA
-7
-6
-6
EP1S30 1,020-pin FBGA -6
EP1S40 1,020-pin FBGA -6
EP1S60 1,020-pin FBGA -6
EP1S80 1,020-pin FBGA -7
Feature EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G
LEs 10,570 10,570 25,660 25,660 25,660 41,250 41,250
Full-Duplex Transceiver Channels 4 8 4 8 16 8 20
Source-
Synchronous Channels
22 22 39 39 39 45 45
M512 RAM Blocks (512 Bits + Parity) 94 94 224 224 224 384 384
M4K RAM Blocks (4 Kbits + Parity) 60 60 138 138 138 183 183
M-RAM Blocks (512 Kbits + Parity) 1 1 2 2 2 4 4
Total RAM Bits 920,448 920,448 1,944,576 1,944,576 1,944,576 3,423,744 3,423,744
DSP Blocks 6 6 10 10 10 14 14
9-Bit x 9-Bit Embedded Multipliers (1) 48 48 80 80 80 112 112
PLLs (2) 4 4 4 4 4 8 8
Availability Buy Now Buy Now Buy Now Buy Now Buy Now Buy Now Buy Now
Notes:
  1. Total number of 9×9 multipliers. To obtain the total number of 18×18 multipliers per device, divide the total number of 9×9 multipliers by a factor of 2. To obtain the total number of 36×36 multipliers per device, divide the total number of 9×9 multipliers by a factor of 8.
  2. Includes both enhanced PLLs and fast PLLs.
Package Size
(mm x mm)
EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G
672-Pin FineLine BGA®
27 x 27
330 330 426 426 - - -
1,020-Pin FineLine BGA
33 x 33 (1)
- - - 542 542 548 548
Notes:
  1. The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock reference pins for high-speed I/O capability.

Configuration

Device

Number of Devices
EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G
EPC2 3 3 5 5 5 8 8
EPC4 1 1 N/A N/A N/A N/A N/A
EPC8 1 1 1 1 1 1 1
EPC16 1 1 1 1 1 1 1
Device Package Speed Grade
EP1SGX10D 672-pin FBGA -6
EP1SGX25C 672-pin FBGA -6
EP1SGX25D 672-pin FBGA -6
EP1SGX25F 1,020-pin FBGA -6
EP1SGX40D 1,020-pin FBGA -6
EP1SGX40G 1,020-pin FBGA -6