Complete Stratix GX Design Package

Altera's Stratix® GX FPGAs integrate high-speed 3.125-Gbps transceiver technology and the high-performance Stratix FPGA architecture, producing an especially flexible solution that addresses high-speed interface applications. Stratix GX FPGAs support many new high-speed protocols, such as SerialLite, 10 Gigabit Ethernet (XAUI), and PCI Express, and can also be programmed to support custom-defined, proprietary protocols. Additionally, Stratix GX devices provide a high-speed source-synchronous I/O interface to balance the data flow across the device and to support many source-synchronous-based high-speed protocols such as SPI-4 Phase 2 and the RapidIO™ standard. The Stratix GX I/O features include dynamic phase alignment (DPA) circuitry, allowing for simpler board layout and increased performance of up to 1 Gbps per source-synchronous channel. For more details on Stratix GX devices, see the Stratix GX Device home page.

Stratix GX devices support a number of different environments including line side, backplane, and chip-to-chip interfacing. As these new applications can generate a number of design challenges, they often require a high level of support. To this aim, Altera offers a complete Stratix GX design package that provides all the design tools needed to reduce the levels of needed support, ensure design success, and speed time-to-market. A variety of information is now available to assist you, including:

SerialLite

The SerialLite protocol is a lightweight, point-to-point protocol, aimed at reducing footprint, latency, and overhead over other serial protocols. Because it focuses on providing essential functionality through scalability, this new, no-cost protocol serves as a complement to other serial protocols.

SerialLite currently has an aggregate data rate ranging from 500 Mbps to 40.8 Gbps. Future expansion of the platform will extend the aggregate data rate to be virtually unbounded for designers’ needs. The protocol incorporates the physical (PHY) layer and a portion of the link layer.

Signal Integrity Center

Higher bandwidth and faster switching edge rates supported by high-speed transceivers can lead to signal deterioration if not handled properly. The Signal Integrity Center discusses this and other issues and describes how Stratix GX FPGAs and good design techniques can help engineers overcome these problems. The Signal Integrity Center provides links to characterization data and other information on signal modeling and board layout.

Device Literature

Stratix GX documentation, including data sheets, application notes, and user guides, provides application-specific information, highlights device capabilities, and offers design and layout information to ensure optimum performance.

Altera Certified High-Speed I/O Design Partners

To help customers identify consulting firms for high-speed design services, Altera has partnered with a select number of engineering services firms. These Altera Certified High-Speed I/O Design Partners are industry-leading design service providers that use the combination of their FPGA and signal integrity expertise to create high-speed, Stratix GX device-based, system-on-a-programmable-chip (SOPC) solutions.

The Altera Certified High-Speed I/O Design Partners are screened via a rigorous certification process that includes in-depth technical interviews and a thorough assessment of their software tools and lab equipment. After the certification process, Altera trains its support partners with the latest Stratix GX development kit technical information. In addition, partners are directly supported by Altera’s high-speed design team.

Intellectual Property

Altera and Altera Megafunction Partners Program (AMPPSM) partners have created a number of off-the-shelf IP optimized for the Stratix GX architecture. The IP MegaStore™ web site provides solutions for many of the protocols supported by the Stratix GX architecture, enabling ease-of-use and quicker time-to-market. Altera OpenCore® evaluation feature allows you to download and try the IP before committing to its purchase.

Reference Designs

Altera has created a number of papers, design examples, and working reference designs to help designers use Stratix GX FPGAs in a variety of applications and protocols. Details include board and layout guidelines, power supply information, and information on how to configure the transceiver using the Quartus® II design software.

Design Utilities

Altera has produced a number of Stratix GX design utilities, including a power calculator, an ASIC vs. FPGA cost calculator, and pin-out information. Altera also offers further design support guidelines via the Board Design Guidelines Solution Center and the I/O Standards & Interfaces Solutions Center.

Device Modeling

System modeling is an extremely important factor when considering signal integrity and printed circuit board (PCB) design. To fully model the I/O interface, designers can use Altera's SPICE models for 1-Gbps source-synchronous I/O signaling and 3.125-Gbps transceiver modeling (contact your local Altera sales representative for more information), and IBIS models for other I/O interfaces.

Technical Training Courses

Altera also offers complete training courses to help you design quickly with Stratix GX FPGAs.

Altera and Altera Megafunction Partners Program (AMPPSM) partners have created a number of off-the-shelf IP optimized for the Stratix GX architecture. The IP MegaStore™ web site provides solutions for many of the protocols supported by the Stratix GX architecture, enabling ease-of-use and quicker time-to-market. Altera OpenCore® evaluation feature allows you to download and try the IP before committing to its purchase.