Stratix® GX FPGAs give system architects a low-risk path to 3.125-Gbps transceiver applications. Based on Altera's Stratix architecture, Stratix GX devices fuse the industry's fastest FPGA architecture with high-performance multi-gigabit transceiver technology.
The Stratix GX FPGA is supported in Quartus® II software and all major third-party synthesis and simulation tools, available today for implementing multi-gigabit designs. The devices are complemented by board-level simulation tools and Stratix GX FPGA-optimized intellectual property (IP).
Table 1 outlines the Stratix GX device family members and features. Table 2 shows an overview of Stratix GX device packaging and I/O pin counts. Table 3 shows the appropriate configuration devices to use for Stratix GX devices. Table 4 shows the industrial temperature support for Stratix GX devices.
Table 1. Stratix GX FPGA Family Overview
|Full-Duplex Transceiver Channels||4||8||4||8||16||8||20|
|M512 RAM Blocks (512 Bits + Parity)||94||94||224||224||224||384||384|
|M4K RAM Blocks (4 Kbits + Parity)||60||60||138||138||138||183||183|
|M-RAM Blocks (512 Kbits + Parity)||1||1||2||2||2||4||4|
|Total RAM Bits||920,448||920,448||1,944,576||1,944,576||1,944,576||3,423,744||3,423,744|
|9-Bit x 9-Bit Embedded Multipliers (1)||48||48||80||80||80||112||112|
|Availability||Buy Now||Buy Now||Buy Now||Buy Now||Buy Now||Buy Now||Buy Now|
- Total number of 9×9 multipliers. To obtain the total number of 18×18 multipliers per device, divide the total number of 9×9 multipliers by a factor of 2. To obtain the total number of 36×36 multipliers per device, divide the total number of 9×9 multipliers by a factor of 8.
- Includes both enhanced PLLs and fast PLLs.
Table 2. Stratix GX Device Package and Maximum User I/O Pins
(mm x mm)
672-Pin FineLine BGA®
27 x 27
1,020-Pin FineLine BGA
33 x 33 (1)
- The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock reference pins for high-speed I/O capability.
Table 3. Appropriate Configuration Devices for Stratix GX FPGAs
|Number of Devices|
Table 4. Stratix GX Device Industrial Temperature Support
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