Stratix GX FPGA Family Overview

Stratix® GX FPGAs give system architects a low-risk path to 3.125-Gbps transceiver applications. Based on Altera's Stratix architecture, Stratix GX devices fuse the industry's fastest FPGA architecture with high-performance multi-gigabit transceiver technology.

The Stratix GX FPGA is supported in Quartus® II software and all major third-party synthesis and simulation tools, available today for implementing multi-gigabit designs. The devices are complemented by board-level simulation tools and Stratix GX FPGA-optimized intellectual property (IP).

Table 1 outlines the Stratix GX device family members and features. Table 2 shows an overview of Stratix GX device packaging and I/O pin counts. Table 3 shows the appropriate configuration devices to use for Stratix GX devices. Table 4 shows the industrial temperature support for Stratix GX devices.

Table 1. Stratix GX FPGA Family Overview

Feature EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G
LEs10,57010,57025,66025,66025,66041,25041,250
Full-Duplex Transceiver Channels484816820
Source-
Synchronous Channels
22223939394545
M512 RAM Blocks (512 Bits + Parity)9494224224224384384
M4K RAM Blocks (4 Kbits + Parity)6060138138138183183
M-RAM Blocks (512 Kbits + Parity)1122244
Total RAM Bits920,448920,4481,944,5761,944,5761,944,5763,423,7443,423,744
DSP Blocks661010101414
9-Bit x 9-Bit Embedded Multipliers (1)4848808080112112
PLLs (2)4444488
AvailabilityBuy NowBuy NowBuy NowBuy NowBuy NowBuy NowBuy Now

Notes:

  1. Total number of 9×9 multipliers. To obtain the total number of 18×18 multipliers per device, divide the total number of 9×9 multipliers by a factor of 2. To obtain the total number of 36×36 multipliers per device, divide the total number of 9×9 multipliers by a factor of 8.
  2. Includes both enhanced PLLs and fast PLLs.

Table 2. Stratix GX Device Package and Maximum User I/O Pins

Package Size
(mm x mm)
EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G
672-Pin FineLine BGA®
27 x 27
330330426426---
1,020-Pin FineLine BGA
33 x 33 (1)
---542542548548

Note:

  1. The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock reference pins for high-speed I/O capability.

Table 3. Appropriate Configuration Devices for Stratix GX FPGAs

Configuration
Device
Number of Devices
EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G
EPC23355588
EPC411N/AN/AN/AN/AN/A
EPC81111111
EPC161111111

Table 4. Stratix GX Device Industrial Temperature Support

Device Package Speed Grade
EP1SGX10D672-pin FBGA-6
EP1SGX25C672-pin FBGA-6
EP1SGX25D672-pin FBGA-6
EP1SGX25F1,020-pin FBGA-6
EP1SGX40D1,020-pin FBGA-6
EP1SGX40G1,020-pin FBGA-6

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