Stratix GX High-Performance Architecture

The Stratix™ GX architecture has two distinctly different functional regions that seamlessly work together: gigabit transceiver blocks and a general-purpose FPGA logic array. See Figure 1.

Figure 1. Stratix GX Architecture

3.125-Gbps Transceiver Technology

The high-performance, programmable Stratix GX architecture contains up to 20 independent, full-duplex channels that support serial bit rates up to 3.125 Gbps. Optimized for encoded, clock data recovery (CDR)-based interfaces such as 10 Gigabit Ethernet XAUI, Gigabit Ethernet, InfiniBand, and SONET/SDH, the gigabit transceiver block supports rapidly emerging, high-speed, data-intensive applications.

Each gigabit transceiver block has circuitry that ensures smooth, seamless data transfer from the block to the rest of the device for processing and manipulation. This circuitry prevents data bottlenecks that can degrade performance and reduce data bandwidth. The logic array and gigabit transceiver block can exchange data as an 8-, 10-, 16-, or 20-bit bus.

The gigabit transceiver block has serialization/deserialization (SERDES) and multiplexing/de-multiplexing circuitry that translates the high-speed serial input stream to a width and frequency suitable for processing within the logic array. Additionally, each gigabit transceiver block has phase-locked loops (PLLs) that multiply or divide the incoming reference clock to serialize or deserialize the outgoing or incoming data. The PLLs also provide clock signals for the functional blocks within the gigabit transceiver block. The architecture can resolve small differences between the phase and frequency of the logic array and external reference clock entirely within the gigabit transceiver block.

Maximized Interconnect Performance

Like Stratix devices, Stratix GX devices have a MultiTrack™ interconnect with DirectDrive™ technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths used for communication within and between distinct design blocks. DirectDrive technology is a proprietary, deterministic routing technology that ensures identical routing resource usage for any function, regardless of its placement within the device. This technology greatly simplifies the system integration stage of block-based designs by eliminating the often time-consuming system re-optimization process that typically follows design changes and additions.

These two architectural advances give designers the technology to freely add, modify, and move various portions of their design without negatively affecting design performance.

Clock Networks for Many Needs

The MultiTrack interconnect structure is complemented by an advanced, low-skew clock network for clock distribution within the device, providing access to up to 22 clock domains per region. Each Stratix GX device features up to 16 global clock networks that span the entire general-purpose logic array, feeding all architectural structures. Internal logic, PLL outputs, or device input pins can drive global clocks. Additionally, you can use global clocks for other device-wide signals with large fan-outs such as asynchronous clears and clock enables, as shown in Figure 2.

Figure 2: Stratix GX Global Clock Distribution

Internal logic, PLL outputs, or device input pins can drive the four regional clock networks in each device quadrant. These clock networks provide the shortest paths with the least amount of skew within the quadrant, making them ideal for localized functions.

Stratix GX devices have fast regional clock networks for high fan-out signals within a quadrant or half-quadrant in larger devices. Separate input pins or signals from the peripheral I/O bus drive these clock networks.

Each device has up to 40 unique clock networks; any node can be driven by up to 22 independent clocks.

In addition to the clock networks described above, Stratix GX gigabit transceiver blocks feature separate clock distribution resources that directly connect to the clocking resources of the device logic array. This architecture ensures maximum flexibility for reference clock generation, clock domain translation, and multi-channel functionality. Refer to the Stratix GX Device Data Sheet for more information on gigabit transceiver block clock distribution resources.