With the inclusion of dynamic phase alignment (DPA) circuitry, Stratix™ GX devices offer enhanced support for source-synchronous protocols. The enhanced source-synchronous channels on Stratix GX devices support 1 Gbps data transfer, while the dedicated DPA circuitry simplifies printed circuit board (PCB) design by eliminating signal-alignment issues introduced by clock-to-data skew. Stratix GX devices support a wide array of high-speed protocols, including the 10 Gigabit Ethernet (XSBI), SFI-4, POS-PHY Level 4 (SPI-4 Phase 2), HyperTransport™, RapidIO™, Network Packet Switching Interface (NPSI), and UTOPIA IV standards (as shown in Table 1).
Designers can use Altera® intellectual property (IP) cores to bridge high-speed interfaces through the Atlantic™ interface. In addition, Stratix GX devices can support several high-bandwidth interfaces at once in one device for an unparalleled bridging solution.
Table 1: Standard Interfaces Supported in Stratix GX Devices
|Maximum Bandwidth (Gbps)||10||10||10||10||6.4||16||10|
|Data (Bus Width)||16||16||16||8, 16||8, 16||
|Maximum Data Rate (Mbps)||1,000||622.08||644.53||1,000||800||1,000||415|
|Maximum Clock Rate (Mbps)||500||622.08||644.53||500||400||500||415|
Used in 10-Gbps systems, including C-192 SONET/SDH and 10 Gigabit Ethernet applications, the POS-PHY Level 4 standard interfaces cell and packet transfers at 10-Gbps between physical (PHY) and link layer devices. Stratix GX device DPA circuitry eliminates clock-to-channel and clock-to-clock skew requirements by continuously aligning a sampling clock with the incoming data. Features such as TriMatrix™ memory, advanced phase-locked loop (PLL) technology, and double data rate (DDR) I/O capabilities, combined with the Stratix GX family's advanced differential I/O capabilities, deliver a 1-Gbps POS-PHY Level 4 solution. For more details on DPA see the Stratix GX Source-Synchronous Signaling web page. For more details on Altera's SPI-4.2 solution, visit the System Packet Interface Level 4 (SPI-4) Phase 2 web page.
SFI-4 is an Optical Interworking Forum (OIF) standard used in an OC-192 SONET system to link the framer and the serializer/deserializer (SERDES). Stratix GX devices support the required data rates of 622.08 Mbps, along with the required 1:1 relationship between clock frequency and data rate. The Stratix GX differential I/O PLL was designed to support these high clock frequencies. Higher data rates are also supported to accommodate system overhead. Stratix GX SFI-4 support extends the reach of high-density programmable logic from the backplane to physical layer devices, providing designers with a system-on-a-programmable-chip (SOPC) solution.
Based on the SFI-4 standard, the 10 Gigabit Ethernet XSBI protocol is a 16-bit LVDS interface used to connect the physical coding sublayer (PCS) and physical medium attachment (PMA) sublayers that are common to a family of 10-Gbps physical layer implementations, collectively known as 10GBASE-R. Stratix GX devices support the required data rates of up to 644.53 Mbps, along with the required 1:1 relationship between clock frequency and data rate. The Stratix GX differential I/O PLL was designed to support the high clock frequencies required for this 1:1 relationship. XGMII is another 10 Gigabit Ethernet interface standard that is supported in Stratix GX devices through the use of the HSTL I/O standard.
HyperTransport technology is a high-speed, high-performance, point-to-point link technology primarily used as a processor interface. Stratix GX differential I/O buffers have been designed to support the specific requirements of the physical layer of HyperTransport technology, including the requirements for a center-aligned clock (with respect to the transferred data) and DDR I/O signaling.
The RapidIO interconnect architecture was designed to link network processors, digital signal processing (DSP) devices, and other peripheral devices. It is a high-performance, packet-switched interconnect technology that can exceed 10-Gbps throughput by the use of LVDS links. Stratix GX devices support the 500-MHz clock frequency and 1 Gbps data rate through their DDR I/O capabilities.
The streaming version of the CSIX interface, called NPSI, is being designed to facilitate 10 Gbps data exchange between traffic managers and switch fabrics. Its design is primarily based on SPI-4.2, but has not yet been standardized. The current CSIX-L1 standard is based on HSTL links. To support 10 Gbps data transfer, the CSIX-L1 bus width needs to be 64 bits wide and clocked at 250 MHz. Both the NPSI and CSIX-L1 interfaces are compatible with Stratix GX devices.