SRAM Support in Stratix GX Devices

SRAM is a transistor-based memory technology that does not require refresh cycles during operation. SRAM devices are generally more expensive to manufacture than comparable dynamic random access memory (DRAM) devices and were originally developed for PC cache applications. SRAM devices are widely used in networking applications because of their high performance capabilities.

Stratix™ GX devices support interfaces with the following four types of SRAM devices at speeds of up to 200 MHz

  • Double data rate (DDR)
  • Quad data rate (QDR)
  • QDRII
  • Zero-bus turnaround (ZBT)

Pipeline & Flow-Through Devices

Synchronous SRAM devices are capable of either pipelined or flow-through functionality. Pipelined SRAM devices incorporate registered outputs as shown in Figure 1, resulting in an extra clock cycle of access latency for read operations. These devices are capable of reaching higher operating frequencies, making them suitable for high-performance systems.

Figure 1: Pipeline Synchronous SRAM Functional Block Diagram (1)

In contrast, flow-through SRAM devices have unregistered outputs as seen in Figure 2. Flow-through SRAM devices are typically used in mid-performance systems but do not have output latency, making them ideal for applications that require faster initial read operations

Figure 2: Flow-Through Synchronous SRAM Functional Block Diagram (1)

Note to Figures 1 & 2:
(1) Source: Texas Instruments, Inc.

DDR SRAM Devices

Older pipeline and flow-through devices synchronize all data transactions to the positive edge of the system clock. Newer DDR SRAM devices were developed to double the total memory bandwidth by accepting data transactions on both the rising and falling edges of the system clock. Data is read and written from a single, common bus, making DDR SRAM devices ideal for applications that require consecutive reads or writes. All inputs to the DDR SRAM devices must meet timing requirements based on a master clock pair. Another clock pair synchronizes data outputs from multiple DDR SRAM devices to a single, common clock at the memory controller. The DDR SRAM device can drive out an optional third clock pair with the data to speed up data capture at the memory controller.

QDR & QDRII SRAM Devices

QDR and QDRII SRAM devices further expand memory bandwidth by allowing four independent data transactions on every clock cycle. This is enabled through the use of two separate data buses and a single, common address bus. Each data bus runs at double data rate, and since input data is separated from output data, simultaneous read and writes may occur. QDR and QDRII SRAM devices use a similar clocking scheme as in DDR SRAM devices. QDR and QDRII technology is being developed by the QDR Co-Development Team, comprised of Cypress Semiconductor, Micron Technology, Integrated Device Technology, Samsung, NEC, and Hitachi. For more information, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices (PDF)

ZBT SRAM Devices

The ZBT architecture is a synchronous memory technology developed by Micron Technology, Integrated Device Technology, and Motorola to provide users with 100% bus utilization by eliminating idle bus turnaround cycles. Older, pipelined and flow-through burst SRAM devices require one to two extra deselect clock cycles (also known as idle or NOP cycles) to avoid contention when transitioning from a write to a read operation and vice versa, effectively increasing individual transaction times. Figure 3 illustrates the reduction in data transfer efficiency caused by the extra deselect cycles when interfacing with flow-through burst SRAM devices. In contrast, Figure 4 illustrates 100% bus utilization that is achieved when interfacing with ZBT SRAM devices. ZBT SRAM devices are ideal for applications that require frequent switches between read and write operations.

Figure 3: Flow-Through Burst Timing Waveforms (1)

Figure 4: ZBT SRAM Timing Waveforms (1)

Note to Figures 3 & 4:
(1) Source: Micron Technology, Inc.

Applications

SRAM devices are optimized for use in high-performance networking and telecommunications applications. Figure 5 illustrates an example of a third-generation (3G) wireless network that uses ZBT SRAM devices in switching functions.

Figure 5: Packet Voice & Data Path Functional Blocks

Intellectual Property

Altera offers fully customizable intellectual property (IP) megafunction controller cores to make designing with Stratix GX devices easier: