The Nios® II family of embedded processors is based on the highly successful first-generation Nios processor and delivers three processor cores to address an even wider range of embedded processing applications. Designers can choose from a high-performance core (over 200 Dhrystone MIPS (DMIPS)), a low-cost core (as little as 35 cents in logic), or a performance-/cost-balanced standard core. The Nios II family of processors addresses tasks such as:
- Implementing complex state machines
- Off-loading existing processors
- Performing I/O and data-processing tasks
- Configuring FPGAs remotely
- Accelerating digital signal processing (DSP) algorithms
The combination of the advanced architectural features of Stratix® GX FPGAs and the enhanced performance of Nios II embedded processors offers the processing power required for today's high-bandwidth systems. With up to 41,250 logic elements (LEs) available in the largest Stratix GX devices, multiple Nios II processors can easily fit into a single Stratix GX device, which satisfies the needs of networking, telecommunications, digital signal processing (DSP), and mass storage applications. Figure 1 shows an example of multiple Nios II processors within a single Stratix GX FPGA in a packet-processing networking design.
FPGA Device Architecture
The Stratix GX FPGA architecture enhances the Nios II embedded processor's ease-of-use and performance. The Stratix GX device's innovative MultiTrack™ interconnect structure improves overall system performance of the Nios II processor to over 150 MHz.
To illustrate this flexible structure, consider a Nios II design example that includes a Nios II/s standard configuration processor core (compiled without a Joint Test Action Group (JTAG) debug core), a JTAG UART, a serial UART, an Ethernet device interface, several I/O peripherals (seven-segment display and LCD module), interface to 8 Mbytes of off-chip flash, interface to 1 Mbyte of off-chip SRAM, and 64 Kbytes of on-chip RAM implemented in a Stratix GX EP1SGX40 device. This design utilizes 3,104 LEs (only 7% of the total available LEs in the device), two M512 RAM blocks (out of 384 available), 11 M4K RAM blocks (out of 183 available), and eight 9x9 multipliers (out of 112 available). This shows that the Stratix GX device allows resource-efficient implementation of complex systems.
The Stratix GX device's TriMatrix™ memory addresses all the memory needs of a typical system-on-a-programmable-chip (SOPC) system. The Nios II processor can access 64 Kbytes of memory per M-RAM block for both data and instruction storage. The Nios II CPU also features an optional, configurable instruction and data cache. Users can add instruction or data caches sized from 512 bytes to 64 Kbytes. Additionally, the abundant TriMatrix memory blocks can implement on-chip cache memory for accelerating off-chip memory access and significantly increasing software performance in embedded systems.
The M-RAM blocks can be cascaded to provide up to 256 Kbytes of memory in the Stratix GX EP1SGX40 FPGA for the Nios II processor. The redesigned I/O buffers in Stratix GX FPGAs feature on-chip termination and support for different I/O standards (e.g., SSTL II), which enable high-speed data access to and from external memory devices such as double data rate (DDR) SDRAM and quad data rate (QDR) SRAM devices.
The Nios II processor also takes advantage of other unique Stratix GX hardware features. Nios II designers can implement multiplication operations entirely in hardware, which harness the multipliers in the Stratix GX FPGA family's embedded DSP blocks. This feature increases multiplier performance and reduces the number of LEs consumed compared to previous device family implementations. (For example, when a multiplication operation is implemented in an APEX™ device, it executes in two clock cycles and consumes 370 LEs for a 16x16 integer multiplication. In a Stratix GX FPGA, the same operation can be implemented in two DSP blocks without using any additional LEs and be executed in only one clock cycle.)
The embedded DSP blocks in the Stratix GX device architecture provide the perfect complement to Nios II custom instructions and hardware acceleration units. DSP designers can now create DSP algorithms and complex math routines in high-performance hardware DSP blocks and access them as regular software routines or implement them as custom instructions to the Nios II CPU. (For example, in a voice-over-IP (VOIP) application, an echo-cancellation algorithm can be implemented in hardware and directly executed in software using a custom instruction. This gives designers the flexibility and portability of high-level software design, while maintaining the performance benefits of parallel hardware operations in FPGAs.)
Stratix GX Devices & Nios II Processors: Complete SOPC Solution
The Stratix GX architecture is ideal for the block-based design methodology that is required for designing large systems using pre-optimized intellectual property (IP) modules or re-using existing design modules.
Altera's SOPC Builder automated system development tool provides designers with a powerful platform for composing bus-based systems out of common system components such as processors, peripherals, and memory interfaces. SOPC Builder-generated systems (such as the one shown in Figure 2) are pre-optimized IP blocks that benefit significantly from the Stratix GX architecture.
A Stratix GX designer can use SOPC Builder to add system components without any substantial impact on system performance; this is possible because of Quartus® II software's Logic Lock Region design methodology feature. SOPC Builder also creates a simulation environment with a testbench for the customer hardware, and can be used to launch the Nios II Embedded Design Suite (EDS).
SOPC Builder provides many customizable peripherals that enable designers to create a completely functional system from a concept in minutes. These peripherals include:
- Interrupt controllers
- Direct memory access (DMA)
- Parallel I/O blocks
- Serial interfaces
- Memory interfaces
The Nios II IDE is a complete software development environment that handles all software development tasks, such as program editing, compiling, and debugging.
The Nios II peripherals and interfaces web page has more details on the peripherals available for the Nios II processors.