Stratix® GX devices integrate high-speed 3.125-Gbps transceiver serializer/deserializer (SERDES) technology with the industry's most advanced FPGA architecture. Historically, designers have used high-speed transceivers strictly in structured line-side applications; now, with multi-gigabit transceiver blocks embedded in FPGAs, designers can use transceivers in a host of new systems that require flexibility, fast time-to-market, high performance, and top-of-the-line features. The Stratix GX multi-gigabit transceiver block has many features that simplify the implementation of standard and custom high-speed protocols.
Multi-Gigabit Transceiver Block Highlights
- Supports all frequencies from 622 Mbps to 3.125 Gbps
- Has 4 independent 3.125-Gbps full-duplex channels per block, with up to 20 channels (in 5 blocks) per device
- Supports 10 Gigabit Fibre Channel at 3.1875 Gbps
- Integrates SERDES, clock data recovery (CDR), pattern detector, word aligner, rate matcher, channel aligner, 8B/10B encoder/decoder, and synchronizer functions
- Has low power consumption, and uses only 450 mW per 4-channel gigabit transceiver block (150 mW for a single channel, which includes the multi-gigabit transceiver block overhead)
- Supports dynamic programmable pre-emphasis, equalization, and differential output voltage (VOD) settings in I/O buffers
- Support for the SerialLite protocol, a lightweight point-to-point serial protocol
- Differential on-chip termination for moderate performance signals
- Fully implements 10 Gigabit Ethernet (XAUI) physical media attachment (PMA) and physical coding sublayer (PCS) functionality
- Supports a flexible clocking topology, including a dedicated transmitter phase-locked loop (PLL) and four receiver PLLs per multi-gigabit transceiver block
- Manufactured on a 1.5-V, 0.13-μm , all-layer-copper CMOS process technology with 1.5-V PCML I/O standard support
- Includes individual transmitter and receiver power-down capability for reduced power consumption during non-operation
- Has built-in self test (BIST) capability, including embedded pseudo-random binary sequence (PRBS) pattern generation and verification
- Has four independent loopback paths for system verification
Figure 1 shows a block diagram of the multi-gigabit transceiver block. You can bypass various blocks, if necessary. Refer to the sections after the figure for additional details on each block.
The multi-gigabit transceiver block differential I/O buffers support the 1.5-V PCML I/O standard, and have a variety of features that improve system signal integrity. For example, dynamically reconfigurable programmable pre-emphasis and equalization capabilities tailor the data signal to compensate for signal degradation across the transmission medium. A variety of programmable VOD settings ensure that the drive strength aligns with the line impedance and trace length. Additionally, differential on-chip termination provides the appropriate receiver and transmitter buffer termination for moderate performance signals
Programmable Transmit Pre-Emphasis Block
The transmit pre-emphasis block enables the transceiver (SERDES) to drive longer backplanes, or cables at frequencies above 1 Gbps. At these frequencies, the channel loss is high, and the degradation is apparent as the eye opening closes the further away the signal travels from the transmitter. Pre-emphasis boosts the high-frequency component of the signal to compensate for the attenuation from the transmission line. With programmable pre-emphasis settings, you can select the optimum level (either in software or dynamically via an internal or external signal) for a given transmission line in order to maximize the signal eye opening at the far-end.
Programmable Receive Equalizer Block
The receive equalizer block enables the transceiver (SERDES) to drive longer backplanes, or cables at frequencies above 1 Gbps. At these frequencies, the channel loss is high and the degradation is apparent as the eye opening closes the further away the signal travels from the transmitter. The receiver compensates for high-frequency attenuation characteristics of the transmission line by boosting the high-frequency content of the signal as it passes through the equalizer block. The programmable equalizer level can be optimized (either in software or dynamically via an internal or external signal) for a given transmission line in order to maximize the signal eye opening at the CDR unit input.
Transmitter and Receiver PLLs
Each multi-gigabit transceiver block has one dedicated transmitter PLL and four dedicated receiver PLLs, providing clocking flexibility and supporting a range of incoming data streams. For data transmission and reception, these PLLs generate the required clock frequencies based upon a lower speed input reference clock. Each PLL supports multiplication factors of 4, 8, 10, 16, or 20. Either external reference clocks or a variety of clock sources within the Stratix GX device can drive the PLLs.
Clock Recovery Unit
The CDR extracts the clock from the incoming serial data stream. The recovered clock is then used to sample the serial data stream and to clock the deserializer.
The SERDES block converts the incoming high-speed serial data stream to a lower-speed parallel interface and vice versa. The SERDES block can be configured for an 8-, 10-, 16-, or 20-bit parallel interface.
Pattern Detector Block
The pattern detector block identifies special patterns within the incoming data stream. The pattern detector includes a built-in K28 comma character detection for 8B/10B and an A1A2 pattern detection for SONET. In custom mode, the designer can create a custom pattern.
Word Aligner Block
The word aligner block, in conjunction with the pattern detector, automatically identifies and adjusts to the correct byte boundary. Additionally, the word aligner has a custom mode where byte alignment can be manually controlled from the FPGA core logic.
Rate Matcher Block
In serial based data transfer, the clock frequencies of the transmitting and receiving devices often do not match. This mismatch can cause the data to transmit at a rate slightly faster or slower than the receiving device can interpret. The Stratix GX rate matcher resolves the frequency differences between the recovered clock and the PLD logic array clock by inserting or deleting removable characters from the data stream, as defined by the transmission protocol, without compromising transmitted data. The Stratix GX rate matcher is optimized for systems that use 8B/10B encoded data.
The channel aligner absorbs the channel-to-channel skew associated with implementing a XAUI protocol where quad transceivers are used. The channel aligner de-skews a quad channel to create an Ethernet XGMII interface to the core logic.
The 8B/10B encoder/decoder block converts an 8-bit pattern to a 10-bit pattern and vice versa. The algorithm balances the zeros and ones within the serial data stream to increase the transition density, thereby making it easier for the receiver to recover the serial data.
The synchronizer compensates for the phase difference between the parallel transceiver interface and the FPGA core logic.
The BIST provides a powerful set of diagnostic capabilities to the transceiver. It includes a pattern generator and checker for pseudo-random binary sequence (PRBS) and others. The BIST also features four loopback configurations that can be used for system diagnostics.
Applications and Protocols
You can use Stratix GX multi-gigabit transceiver blocks for a wide variety of applications. The multi-gigabit transceiver block works with a variety of industry-standard protocols, and supports proprietary custom implementations. For more information on Stratix GX applications and the protocols the multi-gigabit transceiver block supports, see the following pages:
- Stratix GX Applications
- Stratix GX Transceiver Protocols
- SerialLite Protocol for Stratix GX Devices
For more information on other protocols that Stratix GX supports, please see the following pages: