APEX 20K Devices: System-on-a-Programmable-Chip Solutions

APEXAPEX: System-on-a-Programmable-Chip Solutions
APEXPLLIPLogic:  MultiCore ArchitectureAPEX: System-on-a-Programmable-Chip Solutions
APEX: System-on-a-Programmable-Chip SolutionsMemoryAPEX: System-on-a-Programmable-Chip Solutions
APEX: System-on-a-Programmable-Chip SolutionsTrue-LVDSPCIOther StandardsAPEX: System-on-a-Programmable-Chip Solutions

The APEX device family ranges from 30,000 to over 1.5 million gates (113,000 to over 2.5 million system gates) and ships on 0.22-µm, 0.18-µm, and 0.15-µm processes. Introduced in 1999, the APEX device family extended Altera's leadership in embedded PLD architectures to new levels of efficiency and performance. APEX devices are uniquely suited for system-on-a-programmable-chip (SOPC) solutions, allowing designers to integrate a system efficiently and use it in a broad range of applications. Designers wishing to leverage Altera’s more enhanced, highest-density, and highest-performance FPGA technology may wish to find out about Intel's Stratix® series of high-end FPGAs.

Intel's APEX 20KC devices combine a 0.15-µm, all-layer-copper interconnect with state-of-the-art features found in APEX 20KE devices. APEX 20KC devices provide performance improvements of 25 percent over competing 0.18-µm-based devices and meet the high-performance needs of the communications marketplace. Additionally, the APEX 20KC MultiCore architecture combines logic and memory for high-density SOPC solutions. Other members of the APEX 20K device family include the 1.8-V APEX 20KE and 2.5-V APEX 20K devices. Figure 1 shows APEX device processes.

Intel offers the following APEX devices:

  • APEX 20KC device overview (1.8 V, Copper)
  • APEX 20KE device overview (1.8 V)
  • APEX 20K device overview (2.5 V)

Figure 1. APEX Device Processes

All-Layer Copper Interconnect Technology

APEX 20KC devices are the first FPGA family to feature all-layer copper interconnect technology. All-layer copper interconnect technology uses copper for all metal layers, optimizing the performance-critical high-speed interconnects typically found in metal layers 1 through 5. Semiconductor devices that use copper for the top two metal layers typically get no significant performance benefits because the top two layers are used for power planes and do not affect the device performance (shown in Figure 2).

Figure 2. Cross Section of Copper Metal Layers

Breakthrough Performance

The performance benefits of the APEX 20KC FPGAs are made possible using copper interconnects that have lower resistance compared to aluminum interconnects. The lower resistance makes copper an excellent conductor of electricity, thereby improving performance by reducing interconnect delays (as shown in Figure 3).

Figure 3. Aluminum and Copper Delay Comparison

Software Support

Quartus® II design software supports the APEX 20K FPGAs and offers new productivity features like the Logic Lock Region incremental design methodology for creating SOPC designs. With Quartus II software and Altera's wide range of intellectual property (IP) megafunctions, designers can minimize cost and overall design complexity, and improve time-to-market, for their integrated-system applications.