IEEE 1532 Hardware Programming Standard

Press Release

The IEEE 1532 in-system programmability (ISP) standard aims to simplify manufacturing support for ISP devices. The IEEE 1532 specification enables concurrent in-system programming of multiple devices in minimum time. The standard builds on the 1149.1 JTAG boundary-scan architecture standard by addressing both silicon and software issues to create a simplified and homogeneous ISP environment. The standard specifies a common software platform for programming a variety of device types, including memory devices and programmable logic devices (PLDs). It enables common system operation for all IEEE 1532-compliant devices on a system board.

The IEEE 1532 standard is complementary to the JEDEC-approved Jam Standard Test and Programming Language (STAPL). The IEEE 1532 standard is a hardware standard that defines the actual ISP algorithm for each device, while Jam STAPL is a software standard that defines the file format that stores the programming information for the chain of devices.

The official IEEE 1532 specification can be obtained from the IEEE Online Catalog & Store.

Altera Supports IEEE 1532 Specification

The first PLD supplier to ship IEEE 1532-compliant devices, Altera was a major participant in the development and approval of the specification and provides complete silicon and software support for the IEEE 1532 programming specification. Table 1 lists the Altera® devices that are IEEE 1532-compliant.

Table 1. Altera Devices Supporting the IEEE 1532 Specification

Devices IEEE 1532-Compliant Devices
CPLDs MAX® II, MAX 7000AE, MAX 7000B
Configuration EPROMs EPC4, EPC8(1), EPC16
  1. EPC8 devices are IEEE 1532-compatible.

In-Circuit Tester Third-Party Support

Various in-circuit tester manufacturers participated in the development of the IEEE 1532 standard, which is supported by Agilent, ASSET Intertech, Corelis, GenRad, Göpel Electronic, JTAG Technologies, and Teradyne.